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Altera_Forum
Honored Contributor I
1,498 Views

how to using USB (CY7C68013) with Cyclone III

Hi, 

 

I have 2 questions regarding Cypress CY7C68013A with Cyclone III. 

Which SLS usb ip is the right one? Does it allow USB to get connected 

to Avalon Bus? 

 

Thanks, 

 

gl888
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11 Replies
Altera_Forum
Honored Contributor I
213 Views

Cypress CY7C68013A is an ancient USB2.0 solution. You should use a newer USB PHY with ULPI when using SLS's USB2.0 IP cores. For example more up to date USB2.0 PHYs are the NXP ISP1504 , MAX14516 or SMSC usb3300. 

 

Cheers, 

MAX
Altera_Forum
Honored Contributor I
213 Views

Hi, Max, 

 

Thanks for your suggestion. 

 

Would you please give me a little bit more light on why ISP1504, 

usb3300, max14516 is better? Do they offer higher bit rate? 

(by the way, I cannot find any information on max14516) 

 

In my application, USB is used as communication path for downloading  

data from PC to DDR2 on FPGA board. There is any embedded NIOSII 

processor. Data rate is important. I may not need the feature of OTG/host. 

Is there any benefit in CY7C68013A since it has a extral 8051? Can I use 

the 8051 to help automate the data transfer through USB and save NIOSII's 

bandwidth? 

 

Best,
Altera_Forum
Honored Contributor I
213 Views

Older UTMI solutions use more board area because there are more lines. I believe some UTMI based USB 2.0 PHYs are becoming obsolete. It is the older way of doing it. The ULPI based ones use only 12 lines to the FPGA (less lines but at higher speeds). I don't know if the 8051 will help you with data transfer throughput but I know the latest SLS IP Core should be able to achieve 300Mbps with the ULPI type USB2.0 PHYs I mentioned. I was originally considering an FX2 solution as well but I opted to go with a more recent ULPI solution. SMSC3316 may be an option too. I think SLS has a snap on board using the ISP1504. 

 

Cheers, 

MAX
Altera_Forum
Honored Contributor I
213 Views

I'm somewhat confused, that CY7C68013 is discussed as an USB PHY. It's actually an USB 2.0 enabled microcontroller with a fast FIFO interface. It can perfectly work with Altera FPGA and can easily achieve full high speed througput, but without needing an USB IP core.

Altera_Forum
Honored Contributor I
213 Views

Once again, many thanks for the information. 

 

Another question, given the USB is used at high data throughput, 

how much involvement from embedded processor (not the one in USB chip, 

but the NiosII in FPGA) is needed in both cases? 

 

1. using ISP1504/usb3300 

2. using cy7c68013a  

 

Does the processor need to response to interrupt at the end of each frame 

to set up data transfer ?  

 

Thanks, 

 

gl888
Altera_Forum
Honored Contributor I
213 Views

The CY7C68013A EZ-USB will not connect directly to the Avalon bus, you will need to write a bit of logic to do that. How much work the NIOS core will have to do will depend on how sophisticated that logic is. 

 

As FvM said, it provides a fast FIFO interface so there's not much for NIOS to do in terms setting up the transfer. 

However, the EZ-USB buffers can't hold more than 4 packets at a time. 

Note that at full speed (12 Mbit/s) each packet can be 512 bytes but at high speed (480 Mbit/s) it's only 64 bytes. 

 

So, a minimal effort solution would require NIOS to read/write data in batches of 4*pktSize or less.  

 

If this is not good enough, you can improve this by making the interface a bit more sophisticated. 

 

You can add some FIFOs of your own to the Avalon/EZ-USB interface to increase the batch size. 

 

Or you can have the Avalon/EZ-USB interface perform DMA transfers directly to the NIOS RAM. In this case, I'd look at EZ-USB's Master mode, I think it should simplify the DMA logic.
Altera_Forum
Honored Contributor I
213 Views

I hear from your question, that you don't necessarily need a soft processor in your application. With the Cypress chip, it won't serve a particular purpose in my opinion.  

 

The available ISP1504 examples are using NIOS II, so it's an easy way to operate the chip. Without a soft processor, the setup and data transfer has to be performed in your HDL design.
Altera_Forum
Honored Contributor I
213 Views

Many thanks for the suggestions. 

 

As for realistic data throughput, may I say there is no obvious 

advantage one vs the other (i.e. CY7C68013a vs. isp1504, or the 

other way around), given that the interface logic has been well  

designed to handle the setup and automatic data transfer (master  

mode with good buffer size)? 

 

Best regards, 

 

gl888
Altera_Forum
Honored Contributor I
213 Views

Yes, I would expect the same. Generally, both chips are representing different concepts. Cypress has implemented a sophisticated method (GPIF) to achieve optimized data transfers even without fast programmable logic. You don't necessarily need it when interfacing a FPGA, but it can still ease your work.

Altera_Forum
Honored Contributor I
213 Views

Hi FVM, 

 

You may be right. I may have confused the CY7C68013a with the Cypress CY7C68000 (USB 2.0 UTMI PHY ) that I was looking at in the past. I just assumed it was a similar UTMI USB2 PHY since the part number looked so silimar and gl888 asked which SLS IP Core he needed in his original question. 

 

gl888, 

 

These two links show the USB2 PHYs on Santa Cruz Daugther Boards that I was referring to: 

 

http://www.slscorp.com/pages/usb2sls.php (http://www.slscorp.com/pages/usb2sls.php

 

http://www.slscorp.com/pages/usb2ulpisls.php (http://www.slscorp.com/pages/usb2ulpisls.php

 

Cheers, 

MAX
Altera_Forum
Honored Contributor I
213 Views

Hi, FvM, Max, and rbugalho, Thanks very much! Those suggestions and information are very very helpful. Best regards, gl888

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