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Altera_Forum
Honored Contributor I
1,027 Views

using stratix II GX transceiver on low data rate..

The specs of startix II GX transceiver development kit says that it can operate from 600Mbps~6Gbps. 

 

Does that mean there is no way it can operate on lower speeds like 100Mbps? (Im talking about I/O pins here). 

I find this hard to digest! 

 

I still dont have the board thats why I cannot check by myself.. 

 

Check the first paragraph here (http://www.altera.com/products/devices/stratix-fpgas/stratix-ii/stratix-ii-gx/features/transceiver/s...)
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15 Replies
Altera_Forum
Honored Contributor I
40 Views

Hi, 

 

If you are talking about transceivers then they must have bit rate restrictions due to CDR circuitry(PLL can only accept a range of input clock frequency). You can prove that by instantiating an LVDS and entering your rates then check the input clock frequency to PLL. 

 

If you are talking about using the lvds pins only then they should accept any data rate up to an allowed maximum. I certainly don't need transceivers for 100 Mbps 

 

Kaz
Altera_Forum
Honored Contributor I
40 Views

LVDS pins? 

which pins exactly? 

or u mean configuring the TX/RX pins to work on general LVDS mode?
Altera_Forum
Honored Contributor I
40 Views

Hi, 

 

I mean the IO pins that you use for the tranceivers can be used as any IO pins. So the notion of tranceivers becomes irrelevant.  

If your data is that low you don't need to think of the fast tranceiver circuitry.  

Treat your data as any serial stream connected to any suitable IO pins(not necessarily in lvds mode unless you want to). You will need to deserialise it within the fpga. 

Don't forget your clock is now needed 

 

kaz
Altera_Forum
Honored Contributor I
40 Views

 

--- Quote Start ---  

Hi, 

 

I mean the IO pins that you use for the tranceivers can be used as any IO pins. So the notion of tranceivers becomes irrelevant.  

If your data is that low you don't need to think of the fast tranceiver circuitry.  

Treat your data as any serial stream connected to any suitable IO pins(not necessarily in lvds mode unless you want to). You will need to deserialise it within the fpga. 

Don't forget your clock is now needed 

 

kaz 

--- Quote End ---  

 

 

Thanx for the clearification. 

Any idea of how to configure my IO pins to different modes (normal mode, transceiver mode.. etc)? or at least a link to a tutorial for such a thing? 

 

Yes, I will be inputting my own clock through the external clock input.
Altera_Forum
Honored Contributor I
40 Views

You may set the IO pin in differential mode using LVDS IO standard in the pin assignment. LVDS can higher than 1Gbps and I think that is good enough for you. 

 

If you must use the transceiver, you can do over sampling for low data rate. e.g, to oversample by 5 times, you send 5 1's for every logic 1 data and 5 0's for every logic 0 data. Usually people use transceiver that way is because they need to dynamically reconfigure the transceiver for multiple data rate so that the circuit can take high and low data rate.
Altera_Forum
Honored Contributor I
40 Views

Hi, 

 

On a further note, if you don't have your data clock available on board then you can use the transmitters at 600Mbps or more by inserting dummy bits. The receiver transmitter must then follow a protocol, either yours or any of available protocols in your tools 

 

kaz
Altera_Forum
Honored Contributor I
40 Views

 

--- Quote Start ---  

Hi, 

 

On a further note, if you don't have your data clock available on board then you can use the transmitters at 600Mbps or more by inserting dummy bits. The receiver transmitter must then follow a protocol, either yours or any of available protocols in your tools 

 

kaz 

--- Quote End ---  

 

 

Thank you for the explaination. 

 

Could u plz elaborate more regarding configuring my IO to LVDS mode?
Altera_Forum
Honored Contributor I
40 Views

Hi, 

 

compile your project then open assignment editor, select the required pins and choose the io standard "lvds" instead of default "LVTTL". 

 

You will need a 100 Ohm termination resistor between the two signals at the input. If you don't have it on board then choose onchip termination if available in your device- select differential lvds termination in the assignment editor 

 

kaz
Altera_Forum
Honored Contributor I
40 Views

 

--- Quote Start ---  

Hi, 

 

compile your project then open assignment editor, select the required pins and choose the io standard "lvds" instead of default "LVTTL". 

 

You will need a 100 Ohm termination resistor between the two signals at the input. If you don't have it on board then choose onchip termination if available in your device- select differential lvds termination in the assignment editor 

 

kaz 

--- Quote End ---  

 

 

Since I am using SMA connectors, it would be difficult to manually connect a 100ohm resistor at the end of the cable. 

 

I just hope the board has the 100ohm settings. Still didnt look for it. 

 

any other options I can use to implement lvds on this development board?
Altera_Forum
Honored Contributor I
40 Views

It seems to me, that some confusion is still present in this discussion, although a lot has been clarified. 

 

The confusion was obvious to me, as you mentioned the SMA connectors. I don't have a board documentation except a photo, but I wouldn't expect any SMA connector wired to a general purpose IO pin at this board. Very clearly, 24 are connected to GX transceivers. The remaining most likely interface clock in- or outputs. 

 

GX transceivers can't be used as regular serial (LVDS) interfaces. Apart from the said minimum bit rate of 600 MBPSs (that may be handled by oversampling), they require DC balanced (8b10b encoded) bit streams, cause they are AC coupled. 

 

So the answer to your original question using stratix ii gx transceiver on low data rate is no, you can't (except for some special cases). And the said board most likely has no other connected IO pins suitable for this purpose.
Altera_Forum
Honored Contributor I
40 Views

 

--- Quote Start ---  

It seems to me, that some confusion is still present in this discussion, although a lot has been clarified. 

 

The confusion was obvious to me, as you mentioned the SMA connectors. I don't have a board documentation except a photo, but I wouldn't expect any SMA connector wired to a general purpose IO pin at this board. Very clearly, 24 are connected to GX transceivers. The remaining most likely interface clock in- or outputs. 

 

GX transceivers can't be used as regular serial (LVDS) interfaces. Apart from the said minimum bit rate of 600 MBPSs (that may be handled by oversampling), they require DC balanced (8b10b encoded) bit streams, cause they are AC coupled. 

 

So the answer to your original question using stratix ii gx transceiver on low data rate is no, you can't (except for some special cases). And the said board most likely has no other connected IO pins suitable for this purpose. 

--- Quote End ---  

 

 

I just do not understand this. 

Please imagine this with me. 

 

What if all what I want the fpga to do is output the same clock that I am inputting. 

Just a simple verilog program to assign an output to be the same as the clock. 

if my clock is around 50MHz, wont the output operate at 50MHz too? (50Mbps)? 

 

I just do not understand how this (600Mbps as minimum) works! I just need the board to do me this simple task i mentioned above. 

 

Please clearify this for me.
Altera_Forum
Honored Contributor I
40 Views

I don't know any details about the board, I see some parts similar to clock drivers on the photo. I assume, you have a manual, it should answer all your questions. 

 

The properties of GX transceivers are discussed in the Stratix II GX manual in detail. I'm in so far familiar to your special question, cause I once considered to use GX receivers on a PLDA board for LVDS input and found, that it can't work.
Altera_Forum
Honored Contributor I
40 Views

I located the board reference manual in the Altera literature section. It's basically, as assumed. Additionally, some IO's are accessible at a 20-Pin debug header, including differential Rx and Tx pairs. But the IO-Bank is apparently supplied with 3.3V and thus not suited for specified LVDS operation conditions, requiring VCCIO of 2.5 V. It may be usable with reduced performance anyway.

Altera_Forum
Honored Contributor I
40 Views

It seems impossible to connect the transceiver because neither the 24 SMA jacks nor the 20-Pin debug header supplied with 2.5V required by LVDS

Altera_Forum
Honored Contributor I
40 Views

 

--- Quote Start ---  

Hi, 

 

On a further note, if you don't have your data clock available on board then you can use the transmitters at 600Mbps or more by inserting dummy bits. The receiver transmitter must then follow a protocol, either yours or any of available protocols in your tools 

 

kaz 

--- Quote End ---  

 

 

What about the receiver? Is there a way to use the CDR in receiver to recover a clock from 100Mbps bit stream?