Arria 10 SerialLite II Design Example v19.1std

cancel
Turn on suggestions
Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.
Showing results for 
Search instead for 
Did you mean: 
363 Discussions

Arria 10 SerialLite II Design Example v19.1std

​This is the Arria 10 SerialLite II design example with 4 lanes at 10Gbps per lane using Arria 10 FPGA development kit (Production Edition). 

Attachments
v19_1std_sl2_design_example_a10.zip
0 Kudos
Version history
Last update:
‎10-31-2019 07:22 AM
Updated by:
Contributors

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.