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Stratix 10 EMIF Debug GUI

Stratix 10 EMIF Debug GUI


Intel FPGA Stratix 10 External Memory Interfaces (EMIF) Debug GUI

The EMIF Debug GUI is to be used with the Intel Stratix 10 External Memory Interfaces or Intel Arria 10 External Memory Interfaces IP and its packaged example design.

  • The following assumes you are using either the DDR3, DDR4, or QDRIV(Arria 10) EMIF example design which includes the EMIF IP as well as its respective example design.
  • Steps to create the example design based on a specific EMIF configuration can be found in Altera's External Memory Interfaces User Guide.


In order to fully unlock the capabilities of the EMIF Debug GUI, you must do two things: 

1. You must ensure that the EMIF Toolkit is enabled for the EMIF IP. (Steps on how to do this can be found in Altera's External Memory Interfaces User Guide.)

  • Under the Diagnostics tab, in Intel Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port: select Add EMIF Debug Interface
  • e/e8/Diagnostics.JPG


Add EMIF Debug Interface

2. Include the following line in your project's Quartus Settings File (QSF):

set_global_assignment -name VERILOG_MACRO "ALTERA_EMIF_ENABLE_ISSP=1"


This QSF assignment will unlock all of the in-system sources and probes the EMIF Debug GUI relies on to function correctly.

Capabilities of the EMIF Debug GUI

  • The Stratix 10 On-Die Termination Tuning Tool helps find the optimal on die termination settings for an External Memory Interface or EMIF.
  • This includes setting the output drive strength, Dynamic ODT, Rtt Nominal, and Rtt Park settings on the memory side.
  • The user can either manually change these termination settings from the original or let the tool iterate through all possible termination combinations to find the "best" setting.
  • It provides information on calibration margin in terms of delay taps and in ps. Allows you to sort margin data based on various criteria.
  • Tool support per DQ bit pass/fail information as well.
  • The DDR Efficiency Calculator can calculate the efficiency and effective bandwidth of the interface.
  • For QDRIV, you can only do manual changes to the memory termination settings.
  • This tool does not support multiple interfaces.

Storing and Opening the Intel Stratix 10 EMIF Debug GUI

8/8b/S10_system_console.PNG

Opening the EMIF Debug GUI

  1. Download the Intel Stratix 10 EMIF Debug GUI
  2. Determine where your script directory is located
  3. Place the EMIF Debug GUI Tcl file in the script directory
  4. Program your device with an image that includes the Stratix 10 EMIF example design
  5. Open Quartus Prime's System Console
  6. Execute gen10_emif_debug_gui.tcl (version 2)


Introductions Tab

1/1d/S10_debuggui_intro.PNG

The Introductions tab will provide brief How To guide for Stratix 10 EMIF IP.

Memory Configuration Tab

1/1a/S10_debuggui_memconf.PNG

The configurations tab will show some information on how you configured the Stratix 10 EMIF IP before generation.

Manual ODT Tuning Tab

6/6e/S10_debuggui_manODT.PNG

In the Stratix 10 DDRx Manual ODT Tuning Tab, you can change the memory termination and drive strength settings by setting them manually 

  • After making selections from the drop down menus, you must run Calibrate & Run Traffic Generator for the new settings to take place.
  • It also provides information on worse case read and write margin with pin information.

Automatic ODT Tuning Tab

c/c1/S10_debuggui_autoODT.PNG

The Stratix 10 Automatic ODT Tuning Tab allows you to sweep through a set of ODS and ODT combinations to quickly find a working setting based on calibration and traffic generator test status

  • You can choose to sweep through all the settings by keeping the options under Lock your ODS, Rtt_WR, Rtt_NOM, Rtt_PARK set to All.
  • Here you can also choose the number of traffic generator test loops you want to run under Traffic Generator Loops.
  • You can lock down a certain ODS or RTT setting so the tool will sweep through a subset of the possible combinations.

e.g. If you lock ODS to RZQ/7, the sweep will not iterate over combinations with ODS = RZQ/6.

e.g. If you just want to run the traffic generator multiple times for one specific combination, lock down your ODS and RTT and choose how many TG loops to run

  • After locking down your set of combinations you wish to run, click Sweep Chosen ODT Settings.
  • The table will show you calibration pass or fail status as well as the ratio of TG passes based on the number of TG loops you have chosen.
  • The table will also include the worst case Read and Write Post-Calibration margins as well as its respective DQ pin.
  • From this it will choose a "Best" ODS/RTT combination (read margin + write margin) and report it in the top table Best Setting based on R/W Margins

Calibration Information Tab

d/df/S10_debuggui_calinfo.PNG

The EMIF Calibration Information tab allows users to see Read and Write margin information as well as the Input and Output delays post-calibration

  • Clicking on Readout Calibration Data will reread the DQ margin and delay information
  • This tab allows users to also sort the read-out margin data based on DQ pin numbers, DQ margin and Delay setting used.

TG Test-DQ Tab

b/b8/S10_debuggui_TG.PNG

This tab allows users to the TG for N number of loops and shows per DQ bit pass/fail result for chosen loops.

  • Clicking on Run TG Test N Times will re-run the calibration and TG test.

DDR Efficiency Calculator

3/3d/S10_debuggui_eff.PNG

The DDR Efficiency Calculator tab allows users to test the efficiency of their controller settings

  • Before the efficiency can be calculated, several hooks and probes must be added to the top level Verilog file of the design. This can be done automatically using the script S10_add_efficiency_probes.tcl which can be downloaded at the bottom of this page. Place this script in the main in the ed_synth subfolder. Then run the script by clicking Tools -> Tcl Scripts, and double clicking on S10_add_efficiency_probes.tcl. This script will add the necessary registers and probes to the top-level Verilog file synth/ed_synth.v. It will also modify the traffic generator test duration parameter from SHORT to MEDIUM to allow for more reliable testing.
  • Once the probes have been added you can re-run the traffic generator by clicking Calibrate & Run Traffic Generator. This will report the total write cycles, total read cycles, and total clock cycles, as well as the efficiency which is equal to (write cycles + read cycles) / (total clock cycles).
  • It will also show Efficiency and Total Effective Bandwidth on Dial,for given controller setting.

Stratix 10 EMIF Debug GUI Tcl File

Intel Stratix 10 EMIF Debug GUI TCL

Script for adding efficiency probes: S10_add_efficiency_probes.tcl

Version history
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Last update:
‎06-26-2019 06:42 PM
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