The EMIF Debug GUI is to be used with the Intel Stratix 10 External Memory Interfaces or Intel Arria 10 External Memory Interfaces IP and its packaged example design.
In order to fully unlock the capabilities of the EMIF Debug GUI, you must do two things:
1. You must ensure that the EMIF Toolkit is enabled for the EMIF IP. (Steps on how to do this can be found in Altera's External Memory Interfaces User Guide.)
Add EMIF Debug Interface
2. Include the following line in your project's Quartus Settings File (QSF):
set_global_assignment -name VERILOG_MACRO "ALTERA_EMIF_ENABLE_ISSP=1"
This QSF assignment will unlock all of the in-system sources and probes the EMIF Debug GUI relies on to function correctly.
Opening the EMIF Debug GUI
The Introductions tab will provide brief How To guide for Stratix 10 EMIF IP.
The configurations tab will show some information on how you configured the Stratix 10 EMIF IP before generation.
In the Stratix 10 DDRx Manual ODT Tuning Tab, you can change the memory termination and drive strength settings by setting them manually
The Stratix 10 Automatic ODT Tuning Tab allows you to sweep through a set of ODS and ODT combinations to quickly find a working setting based on calibration and traffic generator test status
e.g. If you lock ODS to RZQ/7, the sweep will not iterate over combinations with ODS = RZQ/6.
e.g. If you just want to run the traffic generator multiple times for one specific combination, lock down your ODS and RTT and choose how many TG loops to run
The EMIF Calibration Information tab allows users to see Read and Write margin information as well as the Input and Output delays post-calibration
This tab allows users to the TG for N number of loops and shows per DQ bit pass/fail result for chosen loops.
The DDR Efficiency Calculator tab allows users to test the efficiency of their controller settings