Description:
When performing LMT testing on the AvenueCity and ArcherCity platforms, link downtraining to Gen5 was observed during the test regardless of whether Rx(A), Rx(B), or Rx(C) was selected. The issue occurs with a reproduction rate of approximately 40%, meaning that in every 2 to 3 test runs, one will typically experience downtraining. However, this issue has not been observed on the Beechnut platform.
Currently, the only way to run the test without link downtraining is to disable the 'Gen5 Link Degradation' option in the BIOS.
platform configuration->system event log->pcie error enabling->leak bucket feature->Gen5 link degradation <disbale>
Attachment is test log, please help us to solve this issue, thanks!!
Setup:
CPU: GNR_SP(AvenueCity), EMR/SPR(ArcherCity)
BIOS: 107D20(ArcherCity), 30D67(AvenueCity)
LMT Version: LMT_v0p78_PY38
ASPM: Disabled
LMT Script:
Accept_License = True
Run_Scan = False
Run_LMT = True
Path = r'C:\...\pcie_lmt'
Files_Name = "Test1_AddinCardX"
Segment_Count = 1
Execute_Lane_Reversal = False
input_dic = {
"Lane": [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15], # Select the lanes to be margined. i.e. "Lane": [0,1,2,3,15]
"RecNum": 1, # Select 1 for CPU Rx side, 6 for EP Rx side, 2-5 for Retimers Rx
"Dwell_Time": 1, # Time to wait between each step. Default is 1sec by spec
"BDF_DSP": "B69D01F0", # Provide the Bus, Device, Function from Downstream Port
"BDF_USP": "B6aD00F0", # Provide the Bus, Device, Function from Upstream Port
"ErrCnt": 4, # Error Limit Count. Default is 4 by spec
"Num_Time_Steps": "", # Default is ""
"Num_Voltage_Steps": "", # Default is ""
"Segment": 0, # Default is 0 for two-Socket system
"Speed": 5, # Speed at what margining will be performed
}
import sys
sys.path.append(Path)
from LMT import runLMT
import importlib, LMT
importlib.reload(LMT)
from LMT import runLMT
start = runLMT(Accept_License, Files_Name, Run_Scan, Segment_Count, Run_LMT, Execute_Lane_Reversal, input_dic)
連結已複製
