OpenVINO FPGA Custom birstreams

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OpenVINO FPGA Custom birstreams

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I am working with custom Unet architecture, when I load the network I need use the cpu and hetero plugin for the Upsampling/ResizeNearestNeighbor layer. I want to create a custom bitstream for my architecture, achieving a 100% FPGA execution and network correct loading, How can I do it?

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