recently, on comp.lang.fortran the behaviour of various compilers with respect to functions like log() and atan() with complex arguments was discussed. I tried the test programs that were mentioned in that thread (cmplx.sourceforge.io, if you are interested) and found that Intel Fortran returns false for the support of subnormal numbers for all three types of reals. I verified this with the Intel Fortran compiler, version 18, on both Windows and Linux and I wondered what features are missing. Why is it reported that subnormals are not supported, as you do get subnormal numbers. It may simply be some detail in the IEEE standard that is not supported, but I am curious.
In the MXCSR Control/Status Register, bit 6, is DAZ (Denormals Are Zero). FromIntel 64-ia-32 Instruction Reference (Combined Volumes):
10.2.3.4 Denormals-Are-Zeros Bit 6 (DAZ) of the MXCSR register enables the denormals-are-zeros mode, which controls the processor’s response to a SIMD floating-point denormal operand condition. When the denormals-are-zeros flag is set, the processor converts all denormal source operands to a zero with the sign of the original operand before performing any computations on them. The processor does not set the denormal-operand exception flag (DE), regardless of the setting of the denormal-operand exception mask bit (DM); and it does not generate a denormal-operand exception if the exception is unmasked. The denormals-are-zeros mode is not compatible with IEEE Standard 754 (see Section 126.96.36.199, “Normalized and Denormalized Finite Numbers”). The denormals-are-zeros mode is provided to improve processor performance for applications such as streaming media processing, where rounding a denormal operand to zero does not appreciably affect the quality of the processed data. The denormals-are-zeros flag is cleared upon a power-up or reset of the processor, disabling the denormals-arezeros mode. The denormals-are-zeros mode was introduced in the Pentium 4 and Intel Xeon processor with the SSE2 extensions; however, it is fully compatible with the SSE SIMD floating-point instructions (that is, the denormals-arezeros flag affects the operation of the SSE SIMD floating-point instructions). In earlier IA-32 processors and in some models of the Pentium 4 processor, this flag (bit 6) is reserved. See Section 11.6.3, “Checking for the DAZ Flag in the MXCSR Register,” for instructions for detecting the availability of this feature. Attempting to set bit 6 of the MXCSR register on processors that do not support the DAZ flag will cause a generalprotection exception (#GP). See Section 11.6.6, “Guidelines for Writing to the MXCSR Register,” for instructions for preventing such general-protection exceptions by using the MXCSR_MASK value returned by the FXSAVE instruction.
The above is for the SIMD instructions. The FPU appears to differ in that it will accept denormal numbers (but not as operand values), but will not generate them.