Intel® High Level Design
Support for Intel® High Level Synthesis Compiler, DSP Builder, OneAPI for Intel® FPGAs, Intel® FPGA SDK for OpenCL™
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
541 Discussions

Variable latency for HLS streaming interfaces

pavlovconst
Beginner
657 Views

Hi!

I`m testing an HLS component with two explicit streaming interfaces. First interface is input and second is output. Component`s body incorporates if-else statement, and positive branch has computational latency of 36 clocks when I compile it alone.. Negative branch has computational latency of 0 clocks when I compile it alone.

When I compile entire component I expect to get variable latency based on what condition has been triggered in if-else statement by the input stream. But I always get latency of 36 cycles.

Is it possible to get variable latency for HLS streaming interfaces?

0 Kudos
1 Solution
BoonBengT_Intel
Moderator
575 Views

Hi @pavlovconst,

 

Thank you for posting in Intel community forum and hope all is well.
For the concept pipeline for hardware design, you can refer to the best practice guide, it has some explaining there.


Another useful section that helps explain on conditional statement can be found in the page #25 in the link above.
Hope that clarify your doubts.

 

Best Wishes
BB

View solution in original post

5 Replies
HRZ
Valued Contributor II
623 Views

Due to the pipelined nature of the circuits generated by the compiler, all if-else statements are implemented as two (or more) same-latency paths with a multiplexer at the end; it is not possible to pipeline variable-latency operations. The only way to achieve what you want is to write your code in some way that the compiler would not pipeline the part of the code that encompasses the if-else statement; putting whole loops or different function calls on the two sides of the statement can sometimes achieve this.

pavlovconst
Beginner
603 Views

@HRZ Thanks for the answer

 


@HRZ  написал (-а):

The only way to achieve what you want is to write your code in some way that the compiler would not pipeline


I wonder if this is possible by any means? Can you suggest some example?

 

Is there any documentation on what code constructs always get pipelined, and which ones don`t?

In my tests, I`ve never seen variable latency in the reports, unless MM interfaces get involved... 

BoonBengT_Intel
Moderator
576 Views

Hi @pavlovconst,

 

Thank you for posting in Intel community forum and hope all is well.
For the concept pipeline for hardware design, you can refer to the best practice guide, it has some explaining there.


Another useful section that helps explain on conditional statement can be found in the page #25 in the link above.
Hope that clarify your doubts.

 

Best Wishes
BB

BoonBengT_Intel
Moderator
492 Views

Hi @pavlovconst,

 

Good day, just checking in to see if there is any further doubts in regards to this matter.
Hope we have clarify your doubts.

 

Best Wishes
BB

BoonBengT_Intel
Moderator
382 Views

Hi @pavlovconst,

 

Good to know that we managed to clarify your doubts, with no further clarification on this thread, it will be transitioned to community support for further help on doubts in this thread, where we will no longer monitor this thread.
Thank you for the questions and as always pleasure having you here.

 

Best Wishes
BB

Reply