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E-class CPUs down clock when AVX is in the execution stack? Is this true, if so why would it?

ssote
New Contributor II
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Do E-class CPUs down clock when AVX in the execution stack? if it does Why?

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McCalpinJohn
Black Belt
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The Core i7 processors that are referred to as "Haswell-E" and "Broadwell-E" are minor variants of the Xeon E5 v3 "Haswell-EP" and Xeon E5 v4 "Broadwell-EP" processors.   These have lower "maximum Turbo" frequencies for each core count when 256-bit registers are being used.

For the Xeon E5 v3 ("Haswell-EP") processors, the maximum Turbo frequencies with and without the use of 256-bit registers are documented in Tables 2 and 3 of "Intel Xeon Processor E5 v3 Product Family: Processor Specification Update" (Intel document 330785-010, February 2016). The values in Table 2 (without 256-bit instructions) are the same values that one can read from the hardware registers (MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1) described in Chapter 35 of Volume 3 of the Intel Architectures SW Developer's Manual.

The "specification update" for the Xeon E5 v4 ("Broadwell-EP") does not contain a table of maximum Turbo frequencies with 256-bit registers in use.

I have not looked for this information for the Core i7 parts derived from the Haswell-EP and Broadwell-EP processors.  The corresponding "specification update" documents would be a good place to start.  Some of the Haswell-E based Core i7 parts may have the same core count, power envelope, and nominal frequency as a Xeon E5-16xx processor, in which case the values in the Xeon E5 v3 "specification update" might apply.

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Ian_S_Intel
Employee
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Certain AVX workloads may run at lower peak turbo frequencies, or drop below the Non-AVX Base Frequency of the SKU.  This type of behavior is due to power, thermal, and electrical constraints.
 
A white paper was released for E5v3 (Haswell) describing some of these behaviors:
http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/performance-xeon-e5-v3-advanced-vector-extensions-paper.pdf
 
We are currently developing a plan to update our documentation to support AVX-512 and the E5v5 (Skylake) product line.  The concepts described in the Haswell paper remain largely the same.

 

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ssote
New Contributor II
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Tanks for that information. What is AVX offset for? Is there a degradation problem with running a Processor at TJmax.

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