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Beginner
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How many MMX/SSE units in Core-2 Quad

I have a powerful HP comuter with Q9550 (Core 2 Quad CPU). It seems that there is only one MMX/SSE unit shared between all 4 cores.

The reason I think so is the following. I am running a simple program that usses SSE-2.

  • Running 1 thread achieves 300MB/s.
  • Running 2 threads achieves 150MB/s per thread.
  • Running 4 threads achieves 75MB/s per thread.

My laptop with T7250 (Core 2 Duo CPU) exhibits the similar behavior.

Is it true that Core-2 CPUs contain only one MMX/SSE unit?

Thanks!

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Black Belt
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Agner Fog has been keeping his tables up to date:

http://www.agner.org/optimize/instruction_tables.pdf

so maybe you could find some comparisons of the early core 2 quad vs. current CPU generations.

I'm still mystified as to what you were driving at; were you expecting that x87 instructions could execute in parallel with SSE instructions without requiring the same resources?   I think we have reasonable guarantee there is no sharing of program-accessible registers, but it seems clear they do share micro-op execution pipelines.  As to register sharing between instruction modes, that was tried when MMX was introduced, and abandoned when compatible CPUs came on the market with independent register sets.  My personal, barely educated, guess would be that most independent coding for x87 instructions would reside in the rom and not be in dedicated circuitry.

According to my experience, compilers have given up attempting to cope with register pressure in 32-bit mode by using both x87 and simd registers.  Communication between the register sets is impossibly slow, and the design of Windows 64-bit ABI seemed to exclude attempts to do that in X64. Shortage of integer registers is an even worse bottleneck in 32-bit mode.  Intel compilers have dropped the support for combined x87 and SSE mode which was required for P-III and now support P-III and Athlon32 only in x87 mode; that stuff was already obsolescent when the core2 came out.  But I'm going out on a limb in guessing you might have something like this in mind.

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Black Belt
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It seems that there is no freely available info or clearly  stated information about the implementation from high level POV of x87 unit.Afaik Scheduler logic is wired to execution ports and probably one of those ports( Port1?) is responsible for x87 uops.At register file they probably use different  physical registers to hold temp results and constants.

Just guessing.

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Beginner
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Hello....

I have one basic kind of question...

Does XMM registers say XMM0-XMM7 are per core 

or 

each core has its own bank of 8 registers for Intel Sandy Bridge Architecture ?

Thanks,

Chaitali

 

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New Contributor III
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Each logical core has its own set of architectural registers, including vector registers. It cannot be otherwise since concurrent threads would garble each other's state.

 

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New Contributor II
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Chaitali C. wrote:
Does XMM registers say XMM0-XMM7 are per core

per thread (per logical processor in hardware, saved with the thread context XSTATES in software), btw this is XMM0-XMM15 in 64-bit mode

Chaitali C. wrote:
each core has its own bank of 8 registers for Intel Sandy Bridge Architecture ?

each Sandy Bridge core has 144 registers able to act as x87/MMX or XMM/YMM registers (more register file entries than for the architected state alone is required for temporary rename registers) for the two hardware thread contexts, a good source here: http://www.realworldtech.com/sandy-bridge/5/

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Black Belt
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As it was said by the other posters each CPU core has its own set of physical registers to whom architectural registers(software accessible) are "connected". High number of physical registers are used for register renaming, temporaries storage and probably also used to store decomposed floating point values.

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New Contributor II
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iliyapolak wrote:
and probably also used to store decomposed floating point values.

what are you meaning here ?

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Black Belt
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Sorry I made a mistake in my post. I meant component of various algorithms. For example Taylor approximation of sine constants would be probably kept in those registers.

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New Contributor II
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iliyapolak wrote:
I meant component of various algorithms. For example Taylor approximation of sine constants would be probably kept in those registers.

indeed, though in case of high register pressure load+op instructions will be almost as fast since the constants will be kept live in the L1D cache when used in inner loops

with AVX-512 broadcast load + op (aka "scalar memory mode") will be even more efffective for this usage though we miss timing comparisons at the moment

on a side note: strangely the Intel compiler use a lot more load+op for Knights Landing tagets than for Skylake Xeon targets when compiling the very same source code 

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Black Belt
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Do you mean physical register pressure or architectural registers pressure?

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New Contributor II
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iliyapolak wrote:
Do you mean physical register pressure or architectural registers pressure?

I was meaning logical register pressure, i.e. it is generally a good idea to use load+op for constants for polynomial evaluation and to use the registers for temporary variables, particularly with 32-bit code and only 8 XMM/YMM logical registers

 

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Black Belt
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Yes I agree with you, it is wise to do it even for short few terms polynomial evaluation.

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