In the IDIV instruction "Operation" pseudocode (Vol. 2A, page 3-449, document 325462 rev. 091), the 32-bit and 64-bit branches contain errors. I
confirmed these by viewing the rendered PDF (not copy-paste artifacts).
1. Typo in the 32-bit remainder assignment
Printed: EDX := EDXE:AX SignedModulus SRC;
Should be: EDX := EDX:EAX SignedModulus SRC;
2. Typo in the 64-bit remainder assignment
Printed: RDX := RDE:RAX SignedModulus SRC;
Should be: RDX := RDX:RAX SignedModulus SRC;
3. Missing THEN keyword in two branches
The OperandSize = 8 and OperandSize = 16 branches are written as:
ELSE IF OperandSize = N ...
THEN
temp := ...
However, the OperandSize = 32 and OperandSize = 64 branches omit the THEN
keyword — the condition line is followed directly by "temp := EDX:EAX / SRC;"
and "temp := RDX:RAX / SRC;", breaking the IF/THEN structure used by the
other two branches.
Evidence for the correct register pairs (EDX:EAX, RDX:RAX): the "temp := ... / SRC;"
lines immediately above each assignment, Table 3-53 (Dividend column), the
Description paragraph, and the consistent 8-/16-bit cases
("AH := AX SignedModulus SRC;", "DX := DX:AX SignedModulus SRC;").
