Instruction set extensions programming reference, revision 17,

[MarkC_Intel]

An updated instruction set extensions programming reference, revision 17, has been posted here. 

It includes information about:

• Intel® Advanced Vector Extensions 512 (Intel® AVX-512) instructions
• Intel® Secure Hash Algorithm (Intel® SHA) extensions 
• Intel® Memory Protection Extensions (Intel® MPX) 

For more information about the technologies: http://www.intel.com/software/isa

[MarkC_Intel]

If you were having access problems and finding revision 16, the server cache flushed now and you should see revision 17.

[avk1]

A few days ago I've tested a PC with Pentium G3420 and noticed that the last one has an undocumented CPUID flag, 0000_0001.ECX[11]. Can anybody tell me what is it? You see, I've tried to find some info about this flag, but found nothing at all. Thanks in advance :)!

[MarkC_Intel]

According to our documentation person, that bit will be documented in the next release of the SDM.

Thank you for mentioning the omission. 

[avk1]

You're welcome :).
 

[avk1]

Sorry for the silly question, but please can you tell me when approximately will the new version of the document be released? This winter? This spring? This summer?

[MarkC_Intel]

Hi, Judging by the last 2 years, the SDM comes out roughly quarterly.  In this case though, the doc team is currently preparing updates to both the SDM and the instruction set extension programming reference.  They should be posted in within a few weeks.

Software Developers Manuals (SDM): 

http://www.intel.com/sdm

Instruction Set Extension Programming Reference:  

http://www.intel.com/software/isa

[avk1]

Thank you :).

[MarkC_Intel]

The revision 49 of the SDM has been posted.  http://www.intel.com/sdm

Table 3-20 in volume 1 was updated with the new CPUID bit. Unfortunately, Figure 3-6 was not updated this time around.

[avk1]

Thank you, Mark :)!

But the ISEPR still has some omissions - I mean it doesn't describe these CPUID flags in the Table 2.5: CPUID.0000_0001.ECX[1, 2, 12, 13], i.e. TSC-Adjust, SGX, PQM, DFPUCSDS.

Also, the Figure 2.3 still does miss the SDBG flag.

Also, the description that begins on page 2-18 uses decimal notation in "INPUT EAX = xx", whereas it would be better to use hexadecimal one.

[SHIH_K_Intel]

Hi avk

The flags added in ISEPR primiarily addresses features described in the document. Thx

[avk1]

Hi there,

Seems you've forgotten to interpret a few new AVX-512 flags in the 20-th version: AVX512BW&DQ. I suppose, these ones mean the *BW, and *DQ instructions, right?

Also, the AVX-512VL flag sometimes noted without "512", i.e. as "AVXVL."

Cheers.

[MarkC_Intel]

Thanks for the feedback. And yes, it should be AVX512VL.

[avk1]

Hi there,

There are some typos in the revision 21: in Chapters 3.2.5, 3.2.6, and 9.3.2, the "XRSTOR" instruction has mistakenly been named as "XRESTOR." Or is it a new instruction :)?