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Hi everybody,
I'd like to hear from Intel engineers that Latency of a General purpose MOV instruction on any Intel CPUs is 1 clock cycle. For example, I've completed a set of tests for Intel(R) Pentium(R) 4 CPU 1.60GHz and my numbers are as follows:
[ Intel C++ compiler - DEBUG ]
...
Overhead of Assignment: 1.091 clock cycles
...
[ Intel C++ compiler - RELEASE ]
...
Overhead of Assignment: 1.191 clock cycles
...
A C code with assignment looks like:
unsigned __int64 uiClockCycles = __rdtsc();
and a value returned from RDTSC instruction is assigned to uiClockCycles variable with two General purpose MOV instructions, and it means, that 2 clock cycles will be actually spent.
Thanks in advance.
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Interesting proposition.
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>>...Intel® 64 and IA-32 Architectures Optimization Reference Manual ( B )
A chapter about Latency and Throughput for all instructions in that manual looks very outdated and doesn't include information for some CPUs.
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