ippGetCpuFeatures for AVX2 support

[bronxzv]

I'm relying at the moment on inline ASM to check for AVX2 support, but use the IPP function ippGetCpuFeatures to check for AVX and SSEx features.

Using the IPP function is arguably a better solution (simple & clean) than inline ASM, so I have a comment in my code for the AVX2 checks along the line of "use the IPP stuff instead when available"

I'm doing some cleanup these days and I remarked a series of new flags in ippcore.h, but it looks like several of these new flags aren't explained in the latest IPP documentation.

It will be great to have full documentation for the ippCPUID_AVX2 flag, particularly to know if it implies FMA, BMI1, BMI2 etc., is this information available  somewhere ?

[Vladimir_Sedach · Accepted solution]

Why not _may_i_use_cpu_feature() in Intel's immintrin.h.
http://software.intel.com/sites/products/documentation/doclib/iss/2013/compiler/cpp-lin/GUID-ABD6CC8A-7FEE-40FB-ACA0-616DD2A1FD04.htm
 

[bronxzv]

Vladimir Sedach wrote:

Why not _may_i_use_cpu_feature() in Intel's immintrin.h.
http://software.intel.com/sites/products/documentation/doclib/iss/2013/c...

Thank you for the advice, I overlooked this function, I'll have a try.

Note that I don't see AVX2 (256-bit packed int instructions) in the list of input flags.

Also the documentation isn't very extensive, for example are we sure that _FEATURE_BMI implies BMI1 and BMI2 ?

[Vladimir_Sedach]

In icc 13 there is
_FEATURE_AVX2                0x00800000ULL

_FEATURE_BMI (0x00080000ULL) is Intel's mistake.
I think BMI flag means BMI1 + BMI2 if AVX2 flag is set and BMI1 otherwise )))

http://chessprogramming.wikispaces.com/BMI1
http://chessprogramming.wikispaces.com/BMI2

[bronxzv]

Vladimir Sedach wrote:
I think BMI flag means BMI1 + BMI2 if AVX2 flag is set and BMI1 otherwise )))

We can't be sure since as per your link http://chessprogramming.wikispaces.com/BMI2

"Along with AVX2, BMI2 was expected to be part of Intel's Haswell architecture planned for 2013, but is not yet implemented in the first Haswell generation of mid 2013 ^[1]. BMI2 requires bit 8 set in EBX of CPUID with EAX=07H, ECX=0H."
 

[Vladimir_Sedach]

On first call to _may_i_use_cpu_feature() they fill __intel_cpu_feature_indicator_x with all the flags.
This snippet shows how they set _FEATURE_BMI 0x00080000ULL:

000000013F874D2E  mov         eax,7  
000000013F874D33  xor         ecx,ecx  
000000013F874D35  cpuid  
000000013F874D37  mov         dword ptr [rsp+20h],eax  
000000013F874D3B  mov         dword ptr [rsp+24h],ebx  
...
000000013F874D5E  mov         ebx,dword ptr [rsp+24h]  
000000013F874D62  mov         eax,ebx  
000000013F874D64  and         eax,108h  
000000013F874D69  lea         rdx,[r10+80000h]  
000000013F874D70  cmp         eax,108h  
000000013F874D75  cmove       r10,rdx  
...
000000013F874E46  mov         qword ptr [__intel_cpu_feature_indicator_x (013F88A050h)],r10  

So BMI means both BMI1 and BMI2 are set.

> "Along with AVX2, BMI2 was expected to be part of Intel's Haswell architecture planned for 2013,
> but is not yet implemented in the first Haswell generation of mid 2013 

is not 100% correct -- I have this mid 2013 Haswell (Intel(R) Core(TM) i7-4700MQ CPU @ 2.40GHz) and it has BMI2.

[bronxzv]

Vladimir Sedach wrote:

On first call to _may_i_use_cpu_feature() they fill __intel_cpu_feature_indicator_x with all the flags.
This snippet shows how they set _FEATURE_BMI 0x00080000ULL:

000000013F874D2E  mov         eax,7  
000000013F874D33  xor         ecx,ecx  
000000013F874D35  cpuid  
000000013F874D37  mov         dword ptr [rsp+20h],eax  
000000013F874D3B  mov         dword ptr [rsp+24h],ebx  
...
000000013F874D5E  mov         ebx,dword ptr [rsp+24h]  
000000013F874D62  mov         eax,ebx  
000000013F874D64  and         eax,108h  
000000013F874D69  lea         rdx,[r10+80000h]  
000000013F874D70  cmp         eax,108h  
000000013F874D75  cmove       r10,rdx  
...
000000013F874E46  mov         qword ptr [__intel_cpu_feature_indicator_x (013F88A050h)],r10

So BMI means both BMI1 and BMI2 are set.

Indeed since "108h" is for bit 3 (BMI1) and 8 (BMI2) set in the cpuid extended features.

Thanks a lot for your deep investigation.

btw I have remarked that _may_i_use_cpu_feature  has a more comprehensive list of flags here : http://software.intel.com/sites/landingpage/IntrinsicsGuide/

[bronxzv]

Vladimir Sedach wrote:

Why not _may_i_use_cpu_feature() in Intel's immintrin.h.
http://software.intel.com/sites/products/documentation/doclib/iss/2013/c...

I now use _may_i_use_cpu_feature instead of ippGetCpuFeatures and inline ASM and this is a lot shorter and cleaner

Though, before to use it for production code I still have a concern: I suppose that when checking for a feature such as AVX and AVX2 _may_i_use_cpu_feature also checks for proper OS support (YMM state support), is it documented somewhere so that I can be 100 % sure ?

I ask because my legacy ASM code was checking for the OSXSAVE flag (same cpuid leaf than AVX) and I was also checking the  ippGetCpuFeatures  value ippAVX_ENABLEDBYOS value with no equivalent in _may_i_use_cpu_feature

[Vladimir_Sedach]

Eric,
I'm afraid, you wont be able to find the doc.
__cpuidex() function would allow you easily do the same as in asm. 
I did it myself (~all _may_i_use_cpu_feature flags), if you're curious, I'd send you the code.

[bronxzv]

Vladimir Sedach wrote:

I'm afraid, you wont be able to find the doc.

I have found this doc.: http://software.intel.com/sites/default/files/article/405250/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family.pdf

it includes an alternate code path for other compilers:

uint32_t fma_movbe_osxsave_mask = ((1 << 12) | (1 << 22) | (1 << 27));

confirms that OSXSAVE is checked which was my last concern

uint32_t avx2_bmi12_mask = (1 << 5) | (1 << 3) | (1 << 8);

confirms your finding that _FEATURE_BMI encompass BMI1 and BMI2