Intel® ISA Extensions
Use hardware-based isolation and memory encryption to provide more code protection in your solutions.
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probable mistake in documentation---please check

Intel 64 and IA-32 Architectures
Software Developers Manual Volume 3A:
System Programming Guide, Part 1, Order Number: 253668-034US, March 2010

Masking Maskable Hardware Interrupts
The fact that the group of maskable hardware interrupts includes the reserved inter-
rupt and exception vectors 0 through 32 can potentially cause confusion. Architectur-
ally, when the IF flag is set, an interrupt for any of the vectors from 0 through 32 can
be delivered to the processor through the INTR pin and any of the vectors from 16
through 32 can be delivered through the local APIC.
I just copied some lines of Intel manual in the above.
It says: "...reserved interrupt and exception vectors 0 through 32..."
Reserved and exception vectors are from 0 to 31!! not 32.
Vector number 32, is a user defined vector as far as I know.
Please let me know if there is a mistake as I said.

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You are correct that this is a somewhat imprecise use of the word "through" and differs from its use earlier in the section. Reserved vectors are 0 - 31. User-defined vectors range from 32 - 255.
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