On Intel processors with hyperthreading support, is there any way to avoid having one thread evict cache lines belonging to the other thread? Ideally, I'd like to split the L1 data cache (and maybe other caches as well) in half, changing it from an 8kB 4-way associative cache to two 4kB 2-way associative cache.
The only reference I've been able to find to controlling caching interaction with hyperthreading is bit 24 of IA32_MISC_ENABLE, which controls whether threads can access entries "owned" by the other thread; this does not satisfy my requirements.
Unfortunately, there is no way to do this on a Hyper-Threading enabled system. The caches are shared resources on HT processors. Other parts of the processor architecture are split between the logical processors when HT is enabled; all three levels of the cache resources are not.