Several changes in Prescott are intended to improve HT performance. For example, the increase in number of Write Combine buffers from 6 to 8 would permit HT threaded applications to write efficiently into 3 array sections within a single loop, where 2 was the previous limit.
For publicity purposes, they may be counting other changes since the original P4, such as the alleviation of the 64K aliasing problem, which could bea severe handicap to HT applications. Now, if you neglect to offset your stacks in a Windows application, for example, you should not immediately run into the aliasing problem. The aliasing problem now would occur with 1MB address intervals, so should not be so pervasive. Increased cache size also is likely to improve the effectiveness of HT in many applications.