Intel® Moderncode for Parallel Architectures
Support for developing parallel programming applications on Intel® Architecture.

HT on the new Prescott processor

ronnyzhang
Beginner
140 Views
Hi, I'm interested in the newly anounced Prescott processor( Pentium 4 extream edition with HT).
But I wonder what's the difference between prescott's HT technology and its original versionbuilt in Pentium 4.
I have been looking through this website, and found these words:
Improved Hyper-Threading Technology, including important enhancements to this innovation that make a single processor act like multiple processors to the operating system
But what is the important enhancements? It seems that Intel hasn't posted it on the site. Maybe someone here can help me. Thanks.

Message Edited by RonnyZhang@hotmail.com on 01-15-2004 07:02 AM

Message Edited by RonnyZhang@hotmail.com on 01-15-2004 07:05 AM

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3 Replies
TimP
Black Belt
140 Views
Several changes in Prescott are intended to improve HT performance. For example, the increase in number of Write Combine buffers from 6 to 8 would permit HT threaded applications to write efficiently into 3 array sections within a single loop, where 2 was the previous limit.
TimP
Black Belt
140 Views
For publicity purposes, they may be counting other changes since the original P4, such as the alleviation of the 64K aliasing problem, which could bea severe handicap to HT applications. Now, if you neglect to offset your stacks in a Windows application, for example, you should not immediately run into the aliasing problem. The aliasing problem now would occur with 1MB address intervals, so should not be so pervasive. Increased cache size also is likely to improve the effectiveness of HT in many applications.
isn-removed938
Beginner
140 Views
Yes,this is one improvement, but not a significant change for just increasing in number of Write Combine buffers from 6 to 8.
Is there a technical paper or manual telling us the architectual improvement of Precott's HT relative to P4?
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