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Local APIC questions,how can all local apics use the same base address to access their registers?

APICs (both local and I/O) are memory mapped devices. The default location for the local APIC is at 0xfee00000 in physical memory. The local APIC will appear in the same place for each processor, but each processor will reference its own APIC

If they use the same physical address, how can each processor reference their own registers like apic id register?
Won't this cause disorder?
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Quoting - magina
APICs (both local and I/O) are memory mapped devices. The default location for the local APIC is at 0xfee00000 in physical memory. The local APIC will appear in the same place for each processor, but each processor will reference its own APIC

If they use the same physical address, how can each processor reference their own registers like apic id register?
Won't this cause disorder?

I think you may be tripped up by your interpretation of the statement "APIC are memory mapped devices".

The more accurate way to describe it may be "memory-mapped I/O (operation) is the programming interface to access APIC registers".

The operation of writing a dword to the physical address that maps to an APIC register does not cause the data to latch onto the bus or update into physical DRAM devices.

local APIC is not a piece of hardware shared by multiple logical processors, each logical processor has its own local APIC. Constrast that with physical memory, which is shared by multiple processors.

Take a look at the basic diagram in chapter 2 of volume 1 of the software developer's manual, fig 2-6 and 2-7, for example. In figure 2-8, there is not enough space to showeach local apicexplicitly, but each of the 8 logical processors has its own local APIC.

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Beginner
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I think you may be tripped up by your interpretation of the statement "APIC are memory mapped devices".

The more accurate way to describe it may be "memory-mapped I/O (operation) is the programming interface to access APIC registers".

The operation of writing a dword to the physical address that maps to an APIC register does not cause the data to latch onto the bus or update into physical DRAM devices.

local APIC is not a piece of hardware shared by multiple logical processors, each logical processor has its own local APIC. Constrast that with physical memory, which is shared by multiple processors.

Take a look at the basic diagram in chapter 2 of volume 1 of the software developer's manual, fig 2-6 and 2-7, for example. In figure 2-8, there is not enough space to showeach local apicexplicitly, but each of the 8 logical processors has its own local APIC.


Do you mean the local APIC intercepts memory references to its registers by using the apic_base MSR to determine
whether the addressis mappedto its registers?


Thank you very much. I have been trapped by this problem for seval days. I searched the Internet,read many articles including the software developer's manual but I did not find my answer.
I should havesent a threadearlieron this forum. Thanks!


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