Intel® Moderncode for Parallel Architectures
Support for developing parallel programming applications on Intel® Architecture.

Making Quad Core to Dual Core

Hello All,
We are using Quad Core processors, and for certain beanchmark we would like to run our application in Dual Core. Due to some hardware dependency, we cannot run it on a dual core PC and we would like to disable 2 cores in the existing Quad Core. Does Intel provides any instruction set such as HALT from which we can disable 2 cores and revert it back with some other instruction sets.

PS: Our application is running on linux and we have our own customised kernel.


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4 Replies
Black Belt
Take your choice among the methods for setting affinity, so that you use just the 2 cores of your choice. On Intel single socket quad core processors, according to BIOS numbering, cores [0,2] and [1,3] are expected to share cache. If your application is threaded by the Intel compiler openmp or parallel options, the environment variable KMP_AFFINITY=compact would make applications with 2 threads run on a single cache, if you haven't tinkered with that part of the kernel.
In Linux, does the BIOS numbering the same as the processor number (or core id) shown on /proc/cpuinfo?

Also if I disable the multicore option from the BIOS, I still see 2 cores from /proc/cpuinfo. Does these two share the L2 or not?

Is there any simple way to tell which two pairs share caches in Linux?
Black Belt
If you have a recent enough kernel, e.g. RH 5.1 or SuSE 10.3 with updates, '/usr/sbin/irqbalance -debug' will look up which cores (according to BIOS numbering) are sharing cache.
A majority of the machines I have seen with Intel BIOS are set up so that there is no sharing of cache among the cores in the first half of the BIOS core number list. There are exceptions. It looks like you will have to puzzle out what your "disable multicore" BIOS option is doing, whether it is the same as booting linux with 2 processors enabled. dmesg may shed some light on it.

The description in this article might be helpful to detect the topology of the core.

I've seen systems with funny core numberings like this:

+----+----+----+----+ +----+----+----+----+

Core | c0| c1| c2| c3| | c0| c1| c2| c3|

OScpu# | 0| 2| 3| 4| | 1| 5| 6| 7|

AffMsk | 1| 4| 8| 10| | 2| 20| 40| 80|

Cache | L1D| L1D| L1D| L1D| | L1D| L1D| L1D| L1D|

| L1I| L1I| L1I| L1I| | L1I| L1I| L1I| L1I|

+----+----+----+----+ +----+----+----+----+

| L2 | L2 | | L2 | L2 |

CmbMsk | 5 | 18 | | 22 | c0 |

+---------+---------+ +---------+---------+

I would therefore not rely on a specific numbering. A quick'n'dirty check to verify if two cores share a cache is to write a test program with false sharing and observe the performance difference when you pin it to two cores.