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Q&A: Software Techniques for Shared-Cache Multi-Core Systems

This is a question received by Intel Software Network Support, along withan answer supplied by the authors of the article linkedbelow:

Q. I have read Software Techniques for Shared-Cache Multi-Core Systems, by Tian Tian and Chu-Pi Shih. I am interested in taking advantage of the speedup obtainable in shared cache multicore systems, and I am encountering skepticism in my organization. The skeptics claim there is not going to be any benefit from using the cache, because the instructions will get cached instead of most of the data. I argue that I think the cache controller and algorithm or policy has knowledge of what is data and what is not, and that it is possible that only data can be cached, and we let instruction prefetch deliver the instructions in the pipeline when they are needed, freeing up cache for valuable data. So if I want to know how to find out what a particular system will behave, do I not need to refer to the cache algorithm or policy? Is this published for specific chipsets? How do I answer these questions?

A. Intel Core Duo Processors come with a private 32KB L1 instruction cache and a private 32KB L1 data cache for each CPU core. So there is no competition between data and instructions at L1 level, and 32KB is quite a lot of instructions!

The shared 2MB L2 cache is unified cache, thus it is shared by both data and instructions. For most applications the L2 cache usage is dominated by data. It is possible to disable L2 cache altogether with some help from BIOS, but there is no mechanism to treat data and instructions differently at L2 cache level, since it is a unified cache.

Using Intel VTune Performance Analyzer, you can investigate and trace L1 and L2 cache events and find out more on what is happening for your application and the pattern of cache usage. The analyzer can also highlight the hot spots that with high cache miss events.

For more information on Intel Smart Cache, please see:
http://www.intel.com/technology/magazine/computing/core-architecture-0306.htm#section6

Chapter 10 of the Intel 64 and IA-32 Architectures Software Developer's Manual also has some overview on cache that you may find helpful:
http://www.intel.com/design/processor/manuals/253668.pdf

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Lexi S.

IntelSoftware NetworkSupport

http://www.intel.com/software

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