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zhangyihere
Beginner
65 Views

Questions about cache line mapping

Hi,all.At present,I am trying to do some modification of the Linux memory management based on the Core Due processor.As I know, each physical memory page will be assigned to some certain cache lines on L2 cache(suppose there is no L3 cache).So, in my work, I'd like to do some modification of the Linux memory management so that the OS will partition the memory according to the mapping between L2 cache and memory.

So,I'd like to understand that in the IA-32 Arch,when paging is uesed,how the L2 cache map the physical memory address into the cache line,especially,the detailed address mapping procedure.

I have read the document Intel 64 and IA-32 Architectures Software Developer's Manuals Volume 3A,especially the CHAPTER 3 PROTECTED-MODE MEMORY MANAGEMENT and CHAPER 10 MEMORY CACHE CONTROL,and scan the other chapters and other manuals at the same location http://developer.intel.com/products/processor/manuals/index.htm.But,unluckily,by now I haven't found the items that give the relative specific explanations.

Do these documents explain the mapping methods between L2 cache and memory? Or will other literatures give me an answer?

Thanks a lot.
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robert-reed
Valued Contributor II
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You suggest you'd lile the OS to partiton the memory according to the mapping between L2 cache and memory. Which L2 cache? If you consider any modern multi-socketed processor system, each socket will have its own L2 cache. Intel Architecture uses set-associative caches (as opposed to full-associative or direct-mapped, see CPU caches) that tend to scatter the mapping from cache across the virtual address space, and each L2 continues to change its mapping on demand. Tracking that varying map in the CPU that is changing it seems to me to be an exercise in frustration, but perhaps I'm missing your point? What is it that you hope to gain?
Dmitry_Vyukov
Valued Contributor I
65 Views

zhangyihere:

So,I'd like to understand that in the IA-32 Arch,when paging is uesed,how the L2 cache map the physical memory address into the cache line,especially,the detailed address mapping procedure.


I think that the procedure is something like:
X - linear address of memory location
C - cache line size
P - number of partitions
S - number of sets

Y = X / C // strip lsb
Z = Y % P // calculate partition number

2 memory locations with equal Z will conflict in cache.
And you can store up to S conflicting memory locations in cache simultaneously. If you have more than S memory locations with the same Z, than some of then will be evicted from cache.

C, P and S is different for every cache level (L1, L2, L3).
You can determine C, P and S parameters via CPUID instruction in the deterministic cache parameter leaf.

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