Hardware simulation (register level) is often only done by the manufacturer using something like Transmeta's Caruso with customized firmware.
Software simulation on the same system can be attained with a Virtualization systems. But most of these are setup to provide multiple seperate virtual systems and do not simulate a single system with multiple cores.
Most operating systemsdo permit multi-threading programs, which to some degree simulate a multi-processor system.
Older Intel processors with HT, to a limited extent, simulate a multi-core processor.
The simulation of Multi-Core processor, or simulation of any processor for that matter, is typically useful only by the manufacturer of the processor when they are testing archetectural features such as new instruction sets, or improved pipelining for "next generation" processors that are in the design phase.
Simulation of processors also serves purpose when a processor is no longer being manufactured and no spares are available. This is not the case with the multi-core processors.
For a end-user, the most suitable route is to purchase a system withthe Multi-Core Processor. This will be more cost effective than acquiring a simulation system (either hardware or software).
You will require the specification of the hypothetical multi-core architecture. This will include the instruction set, cache relationship(s), potentially memory bus configuration(s) and timing information. Instruction pipeline information and other internal features.
With this information at hand, you write what is called an emulator. You would choose a good language for the emulation, C++ (or C) would be a good choice.
You would define a class object that maintains the state of the virtual processor and instantiate as many such processor class objects as you wish to emulate in your simulation. The processor class objects would be initialized according to the level of detail you wish to emulate: e.g. does a processor have multiple cores, do cores within the same processor share the same cache (and how), how memory is shared between processors, etc...
Emulated instructions will likely be performedusing multiple time states with different instructions requiring different numbers of time states, and instructions within a core may be pipelined so more than one instruction in each processor core will be at various states of completion. You would likely have a synchronized time state between all processors but your simulation could permit skewing of the time states if you want to go to that extent in your simulation. Most multi-processors systems have something that is used as a master timing reference such as one timing source for the shared memory Front Side Bus. But this is dependent on your design of the hypothetical archetecture.
Writing such a simulator is a major project.
The next phase would be to adapt a compiler (Open Source C++ like GNU would be a likely candidate) such that it produces object code for this hypothetical processor. Then you would need to write (adapt) a Linker to construct a file containing an execuitable image.
You would also need to implement a rudimentary operating system within your virtual environment. Something like a BIOS. The simulation begins bypopulating some virtual memory with boot code and starts emulation. One of the first things in the emulated boot code is a BIOS call to load the test application. The test application makes BIOS calls to instantiate the additional processors and to start the interpretation.
This is a major undertaking.
There is a class of processors that are used within embedded systems. Embedded processors are "simulated" withina programmabledevice (FPGA). A popular embeded processor is called ARMn (where n is a series number, e.g. ARM7). NIOS is another popular embedded processor. These embedded processors have C/C++ compilers and utilities. It is not unusual for an FPGA to contain multiple processors either running independently or running with shared memory.
The manufacturers of FPGA devices have development platforms such that you can simulate the FPGA totally with software on a PC. Therefore, it might be possible for you to piece together most of what you need by using components of an FPGA development platform.
Check with your Electrical Engineering department to see if they work with FPGA development systems, if so, ask for a demonstration.
Also note that in lieu of writing a software emulator of your hypothetical multi-processor archetecture you can construct the processor(s) within the FPGA or multiple FPGAs and have reasonably good fidelity in the emulation of your hypothetical system.
hi i am a student form Egypt in computer engineering and want a multicore processor simulator source code in c++ language
from where can i get one like that?
thanks for your help and waiting for your reply