Skylake Mesh Frequency

[hpcdkhab]

Dear supporter,

Haswell (i.e. E5 2600 v3) provides a possibility to read out the frequency of the rung bus ( rdmsr -p0 -d  0x704 ). I suspect that the mesh frequency of skylake  can also differ from the core frequency. Is it possible to read that frequency ? I am especially interested in the processors:

skx6130, skx5120,skx6128 and skx6148

Thank you,

Dmitry

[McCalpinJohn]

MSR 0x704 reads the uncore clock, which can be used to measure the average uncore frequency over an interval.

Volume 4 of the Intel Architectures Software Developer's Manual (document 335592) includes a description of MSR 0x620, typically called MSR_UNCORE_RATIO_LIMIT.  Coming out of reset, this contains the upper and lower limits of the uncore ratio (relative to the 100 MHz reference clock) when operating in dynamic uncore frequency scaling mode, and the upper and lower limits can be overwritten to limit the range (including forcing it to a single frequency).  

Two important points:

1. You should write down the original values before modifying them -- I don't know of any way to obtain the original upper and lower limits other than rebooting the system.
2. When operating in a power-limited state, the power control unit will ignore your requested frequency range and set the uncore frequency based on its own ideas of the best distribution of power between the cores and the uncore.

[hpcdkhab]

Dr. Bandwidth, thank you for the information.

Does the register UNCORE_RATIO_LIMIT hold the current frequency, if the cpu in the power-limited state ? I could't find any MSR_U_PMON_UCLK_FIXED_CTR (MSR 0x704 for Haswell) in order to read the uncore clock of skx processors.

Best regards,

Dmitry

[McCalpinJohn]

The UBOX clock counter has not moved -- it is still in MSR 0x704.  You may need to write 0x00400000 to MSR 0x703 to enable the counter.  This is all disclosed in the Xeon Scalable Processor Uncore Performance Monitoring Guide (document 336274).   Sometimes the counters are "frozen" by some other utility and left in that state.  You can unfreeze all the uncore counters by writing 0x200000000000 (set bit 61) to MSR 0x700.  Unfortunately the "freeze bit" (bit 63) is "write-only", so you can't query whether or not the uncore counters are frozen, you can only write to the freeze or unfreeze bits.

MSR 0x620 holds the limit values from power-on reset or as specified by the user -- they are not updated dynamically if the PCU decides that it cannot provide a frequency in the requested range. 

Fortunately MSR 0x704 works fine, so you can compute the average frequency over any interval in which the package does not go into a deep package C state.