I have hopefully a quick question...
I'm using a dual socket quad core (HT) Xeon X5570. It is a NUMA machine with each core having its own L1 and L2 caches and each socket's cores share a single L3 cache on the die. My question revolves around access and coherence specifically with the shared L3 cache.
I'm looking to have the most efficient communication between threads that will only run on cores on the same socket sharing the same L3 cache. I'm looking to do this through having a shared memory block (an array) that is only accessed by threads on the same socket/L3 cache. If only these threads access this array (so no other cores on different sockets will access it), will write backs to main memory be required? I'm intersted in what the specific cache coherency mechanics will be under this scenario?
Thanks for your help.