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Hi
I have to write a program in C for test the different execution time with use of the cache warm or cold.
I have use the directive asm("clflush (%0)"::"r"(m)); for invalidate all the line that contains the address of the vector that i want read (m), but the time of read is substantially the same whitout the flush !
where i wrong ?
i test a dual core duo whit 32 Kb - L1 chace 64 byte line size.
report the code for explain :
for ( i=0; i { asm("clflush (%0)"::"r"(v+i)); }
gettimeofday(&start,NULL);
for ( i=0; i{
sum += compute(v));
}
gettimeofday(&stop,NULL);
thank you !!!!
I have to write a program in C for test the different execution time with use of the cache warm or cold.
I have use the directive asm("clflush (%0)"::"r"(m)); for invalidate all the line that contains the address of the vector that i want read (m), but the time of read is substantially the same whitout the flush !
where i wrong ?
i test a dual core duo whit 32 Kb - L1 chace 64 byte line size.
report the code for explain :
for ( i=0; i
gettimeofday(&start,NULL);
for ( i=0; i
sum += compute(v));
}
gettimeofday(&stop,NULL);
thank you !!!!
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If you have the normal setting of hardware prefetch, flushing cache could affect only the time required to get the first 2 cache lines or so of each page. I suppose that cache miss timing tests would be done with more irregular access patterns. You could look at how it was done with lmbench.
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