hi, Thanks Tim for your answer but if you don't mind i want to know more details. I 'm not understanding exactly what you had wrote. Please can you explain more!!!! (I'm sorry to tell you this, don't you mind if you write in french!!!!!!!!!!) Thanks a lot again.
Supposing that you were using MKL library, which is supplied with icc, you can read in the docs about how it has preferences for certain data alignments. Certain matrix sizes would permit more even division of work among threads with more frequent favorable alignment (16-byte or cache line alignment) so as to reduce time spent in scalar remainder loops. Dependence of performance on special alignments for SSE2 vectorization has been reduced in more recent architecture designs, but is about to increase again with the advent of AVX vectorization with its 32-byte alignment preference.