virtual address aliasing

[stardust496]

Hello,

I am working with Xeon and up processors. Am wondering what happens if I have different virtual addresses that actually map to the same physical address (say I have mmapped things deliberately so that the above happens)

Which caches use physical adresses and which use virtual addresses? If a cache uses virtual addresses and I write something to a virtual address, what is performance hit for the cpu to ensure that if any other virtual address refers to the same physical address, then that cache location is invalidated/updated ?

Thanks!

[Dmitry_Vyukov]

Quoting stardust496

Am wondering what happens if I have different virtual addresses that actually map to the same physical address (say I have mmapped things deliberately so that the above happens)

I am curious how do you do that. Can't you describe it in some detail?

[TimP]

For a 4-way associative cache, typical of Xeon processors, at most 4 mappings which share the same lowest address bits can be accommodated. For conflicts beyond that, cache lines must be evicted. If you want to discuss these topics further, you may wish to consult a textbook such as Hennessey & Patterson and get your terminology synchronized.

[stardust496]

Sorry for not being clear.

What I am doing is mmapping a file in linux. I mmap the same file twice. So now I have two pointers , i.e. two different virtual addresses each of which can be used to write to the same underlying physical pages.

I was wondering how the caching system (in my case xeon processor) deals with such "multiple virtual addresses referring to the same physical address"

I looked at Hennessey and Patterson, and as per their terminology in Appendix C of fourth edition I would like to know if (1) Xeon uses either fully virtually addressed caches or fully physically addressed caches or virtually indexed / physically tagged caches , (2) What are the performance implications for the system to detect and handle virtual aliasing. i.e. is it better for me to avoid such multiple mappings if I can?

If two virtual addresses are at all to alias, then they will both have the same lower 12 bits (assuming 4k page size). Following a hypothetical example from the same Appendix C, the higher 6 of these 12 bits will be used as the index to find the set. And from what TimP is saying, (which I am likely misunderstanding) it seems that once you arrive at the set (which is say 4-way) , it can have 4 different virtual addresses which probably means that the cache is fully virtually addressed. If it were virtually indexed / physically tagged then the system should be able to look at the 4 locations in the set and find out if any of them has the same physical address.

Thanks..

[jimdempseyatthecove]

What you end up with is multiple DTLB's referencing the same physical address. The cache system, excepting for DTLBs,works with physical address. Otherwise, how could you have a unified L3 cache amongst 4/8/16 hw threads (each potentially having different VM mappings).

Your virtual address is mapped via Data Translation Buffer (obtained from Page Table and cached in DTLB) to a Physical Address. The Physical Address is then used by the caching system.

Jim Dempsey