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qing_wang
Beginner
671 Views

When I test AEP memory, I found that flushing a cacheline repeatedly has a higher latency than flushing different cachelines. I want to know what caused this phenomenon. Is it wear leveling mechanism ?

I used clwb instrusion, followed by sfence.

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5 Replies
Franklin_S_Intel
Employee
224 Views

Hello,

 

Thank you for joining our community. Please allow us some time for us to get back with you with a more solid answer on your question. We will follow up with you as soon as possible.

 

Regards,

Franklin S.

Intel Customer Support Technician

Under Contract to Intel Corporation

Franklin_S_Intel
Employee
224 Views

Hello,

 

Would it be possible for you to provide the following:

 

- Detail information about how cacheline is flushed repeatedly (example)?

- Detail information about flushing different cachelines (example)?

- Show the latency differences between above two?

 

Output from following commands:

- dmidecode -t bios

- lscpu

- dmidecode | grep -A4 '^Base Board Information'

- uname -a

- ipmctl show -topology

- ipmctl show -dimm

- ipmctl show -firmware

 

Regards,

Franklin S.

Intel Customer Support Technician

Under Contract to Intel Corporation

Franklin_S_Intel
Employee
224 Views

Hello,

 

This is a follow up to see if you were able to get the information requested before to move forward with your case. Let us know if you have any additional questions or concerns.

 

Regards,

Franklin S.

Intel Customer Support Technician

Under Contract to Intel Corporation

Franklin_S_Intel
Employee
224 Views

Hello,

 

Please notice the following:

 

All DCPMM wear leveling is internal to DCPMM and under control of the DCPMM controller. There is nothing wear level related visible from the host.

 

Generally, if read/write data to & from PMEM, every time flushing the cache, it must wait until the cache is empty before resuming processing.

 

In short, flush if you absolutely have to, but be aware that it can be an expensive operation with respect to throughput.

 

The hardware has been optimized to protect the data in case of unexpected power failure with a feature called ADR

 

Refer to the App Direct transaction flow slide in https://newsroom.intel.com/wp-content/uploads/sites/11/2019/08/Intel-Optane-HotChips-presentation.pd...

 

Regards,

Franklin S.

Intel Customer Support Technician

Under Contract to Intel Corporation

Franklin_S_Intel
Employee
224 Views

Hello,

 

Please let us know if you have any additional questions or concerns and we will be happy to assist you.

 

Regards,

Franklin S.

Intel Customer Support Technician

Under Contract to Intel Corporation

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