Hello,
I'm a beginner just starting to use Intel Quartus Prime for FPGA design, and I've encountered some error messages.
I believe I have assigned all the external I/O ports but I'm still receiving warnings indicating that some pins are unassigned.
I have set my Block Diagram Editor Schematic file (FPGA.BDF) as the Top-Level Entity. I have also used the Pin Planner to assign all the Node Names to their corresponding physical Pin Locations.
I'd like to ask if a 1-to-2 junction, as shown in the diagram above, should not be wired directly like this. If so, how should I handle it?
I'd like to ask if the warning messages, such as the one mentioned, can simply be ignored.
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Warning (169177): 12 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
Info (169178): Pin upstream_clk uses I/O standard 3.3-V LVTTL at K4
Info (169178): Pin downstream_ff uses I/O standard 3.3-V LVTTL at L6
Info (169178): Pin upstream_we uses I/O standard 3.3-V LVTTL at M4
Info (169178): Pin rst uses I/O standard 3.3-V LVTTL at L4
Info (169178): Pin upstream_databus[7] uses I/O standard 3.3-V LVTTL at R3
Info (169178): Pin upstream_databus[6] uses I/O standard 3.3-V LVTTL at P3
Info (169178): Pin upstream_databus[5] uses I/O standard 3.3-V LVTTL at P4
Info (169178): Pin upstream_databus[4] uses I/O standard 3.3-V LVTTL at R5
Info (169178): Pin upstream_databus[3] uses I/O standard 3.3-V LVTTL at P6
Info (169178): Pin upstream_databus[2] uses I/O standard 3.3-V LVTTL at R7
Info (169178): Pin upstream_databus[1] uses I/O standard 3.3-V LVTTL at P7
Info (169178): Pin upstream_databus[0] uses I/O standard 3.3-V LVTTL at N8
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (222013): Relative toggle rates could not be calculated because no clock domain could be identified for some nodes
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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