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ALTPLL Megafunction simulation error

Altera_Forum
Honored Contributor II
‎04-27-2016 12:14 PM
2,268 Views

Hello All, 

 

I am trying to simulate Altera_soft_LVDS megafunction using external PLL using ALTPLL megafunction. If I start simulation in Modelsim tool I am getting this type of errors in transcript 

# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(110): Unresolved defparam reference to 'altpll_component' in altpll_component.bandwidth_type.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(111): Unresolved defparam reference to 'altpll_component' in altpll_component.clk0_divide_by.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(112): Unresolved defparam reference to 'altpll_component' in altpll_component.clk0_duty_cycle.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(113): Unresolved defparam reference to 'altpll_component' in altpll_component.clk0_multiply_by.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(114): Unresolved defparam reference to 'altpll_component' in altpll_component.clk0_phase_shift.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(115): Unresolved defparam reference to 'altpll_component' in altpll_component.clk1_divide_by.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(116): Unresolved defparam reference to 'altpll_component' in altpll_component.clk1_duty_cycle.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(117): Unresolved defparam reference to 'altpll_component' in altpll_component.clk1_multiply_by.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(118): Unresolved defparam reference to 'altpll_component' in altpll_component.clk1_phase_shift.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(119): Unresolved defparam reference to 'altpll_component' in altpll_component.compensate_clock.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(120): Unresolved defparam reference to 'altpll_component' in altpll_component.inclk0_input_frequency.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(121): Unresolved defparam reference to 'altpll_component' in altpll_component.intended_device_family.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(122): Unresolved defparam reference to 'altpll_component' in altpll_component.lpm_hint.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(123): Unresolved defparam reference to 'altpll_component' in altpll_component.lpm_type.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(124): Unresolved defparam reference to 'altpll_component' in altpll_component.operation_mode.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(125): Unresolved defparam reference to 'altpll_component' in altpll_component.pll_type.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(126): Unresolved defparam reference to 'altpll_component' in altpll_component.port_activeclock.# # Region: /lvds_transmitter/DUT_2# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(127): Unresolved defparam reference to 'altpll_component' in altpll_component.port_areset.
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Altera_Forum
Honored Contributor II
‎07-28-2016 08:27 AM
1,396 Views

hello vish2648 

 

I have faced the same problem with you. 

Ｉ　ｔｈｉｎｋ　ｙｏｕ　ａｌｓｏ　ｕｓｅ　ｔｈｅ　ｌｉｂｒａｒｙ　ｉｎ　ｍｏｄｅｌｓｉｍ．（Ｃｏｍｐｉｌｅ->StartSimulation Windows: In "Design" choose the tb file; In "Libraries" SearchLibraries->add: add the suitable library-> OK） 

 

Ｔｈｉｓ　ｐｒｏｂｌｅｍ　ｍａｙ　ｂｅ　ｃａｕｓｅｄ　ｗｈｅｎ　verilog is ｕｓｅd　　ｉｎ　ｔｈｅ　ＩＰ　ｂｕt　ｔｈｅ　ＶＨＤＬ　ｌｉｂｒａｒｙ is choosed．　 

 

ｆｏｒ　ｅｘａｍｐｌｅ　ｌｉｂｒａｒｙ　ａｌｔｅｒａ：　ａｌｔｅｒａ　ｉｓ　ＶＨＤＬ　ｌｉｂｒａｒｙ 

 

 

　　　　　　　　　　　　　　　　　　　　　ａｌｔｅｒａ_ｖｅｒ(*_ver)　ｉｓ　ｖｅｒｉｌｏｇ　ｌｉｂｒａｒｙ． 

 

Ｔｈｏｕｇｈ　ｉｔ　ｉｓ　ｔｏｏ　ｌａｔｅ　ｔｏ　ｗｒｉｔｅ　ｂａｃｋ　ｔｏ　ｙｏｕ． 

 

Ｗｉｓｈ　ｙｏｕ　ｓｏｌｖｅ　ｔｈｉｓ　ｐｒｏｂｌｅｍ． 

 

Ｆｏｒｇｉｖｅ　ｍｅ　ｔｈｅ　ｐｏｏｒ　Ｅｎｇｌｉｓｈ． 

 

Ｍｙｙ　
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Altera_Forum
Honored Contributor II
‎10-06-2016 07:21 AM
1,396 Views

it helps. thanks!

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