Agilex 7 F-tile PCIe questa simulation failed

[tthhuang]

Hello,

I followed ug20332 to generate F-tile PCIe example design and Questa simulation environment but get below error message, does any expert know the issue?

Best regards

** Note: (vsim-3812) Design is being optimized...
# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
# ** Error: ../../../../ip/pcie_ed/pcie_ed_syspll_inst/systemclk_f_300/sim/pcie_ed_syspll_inst_systemclk_f_300_p45yqwy.sv(1432): Module 'ctfb_avmm1_soft_logic' is not defined.
# For instance 'avmm1_ena_inst' at path 'pcie_ed_tb.pcie_ed.syspll_inst.syspll_inst.x_sip'
# ** Error: ../../../../pcie_ed_rp/ip/pcie_top/syspll/systemclk_f_300/sim/syspll_systemclk_f_300_p45yqwy.sv(1432): Module 'ctfb_avmm1_soft_logic' is not defined.
# For instance 'avmm1_ena_inst' at path 'pcie_ed_tb.dut_pcie_tb_ip.dut_pcie_tb.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.u1.rp.inst.dut.syspll_inst.systemclk_f_inst.x_sip'
# Optimization failed
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=2, Warnings=1.
# Error loading design
# End time: 16:40:36 on Apr 25,2024, Elapsed time: 0:01:58
# Errors: 2, Warnings: 1, Suppressed Errors: 2

[wchiah]

Hi,

Thanks for contacting Intel. I'm assigned to support request.

I'll investigate and get back to you soon. Thanks for your patience.

Best regards,

Wincent_Intel

[wchiah]

Hi,

May I know which Quartus version and Questasim version that you are using ?

Regards,
Wincent_Intel

[tthhuang]

I use quartus 23.4 w/ questa2023.3, thanks.

[zutalors]

You might want to check that the above is not due some earlier error (it says Errors: 2), search for Error from the top rather than from the bottom, or you can grep for all the Error in your simulation log file and leave out all the zero errors:

grep Error your-simulation-log-file | grep -v 'Errors: 0'

[tthhuang]

Hizutalors,

Thanks for suggestion, but I have check the log, all the two errors are listed below.

** Note: (vsim-3812) Design is being optimized...
# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
# ** Error: ../../../../ip/pcie_ed/pcie_ed_syspll_inst/systemclk_f_300/sim/pcie_ed_syspll_inst_systemclk_f_300_p45yqwy.sv(1432): Module 'ctfb_avmm1_soft_logic' is not defined.
# For instance 'avmm1_ena_inst' at path 'pcie_ed_tb.pcie_ed.syspll_inst.syspll_inst.x_sip'
# ** Error: ../../../../pcie_ed_rp/ip/pcie_top/syspll/systemclk_f_300/sim/syspll_systemclk_f_300_p45yqwy.sv(1432): Module 'ctfb_avmm1_soft_logic' is not defined.
# For instance 'avmm1_ena_inst' at path 'pcie_ed_tb.dut_pcie_tb_ip.dut_pcie_tb.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.u1.rp.inst.dut.syspll_inst.systemclk_f_inst.x_sip'
# Optimization failed
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=2, Warnings=1.
# Error loading design
# End time: 16:40:36 on Apr 25,2024, Elapsed time: 0:01:58
# Errors: 2, Warnings: 1, Suppressed Errors: 2

[wchiah]

Hi,

I am able to go through the simulation after clean up the environment,
Can you please try it again ?

If not you may try our golden pcie example design through link below
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agf027-and-agf023.html

Regards,

Wincent_Intel

[tthhuang]

Hi Wchiah,

Yes, it works now, thanks for your help.

Best regards

Victor

[wchiah]

Hi

Glad to hear you are able to resolved the problem.

Therefore following our support policy, this thread will be transitioned to community support.

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Regards,

Wincent_Intel

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