Async FIFO 2 Clock code advice - VHDL

[Altera_Forum]

Hi all, 

  I want to ask if someone can advice me an Async FIFO with 2 clocks code in VHDL that works. I know Xilinx provide already build in FIFO IP core, but since I want possibility to migrate my code also to other devices I need a code that I can easy port.    Thank you.

[Altera_Forum]

Altera have a DC fifo megafunction. You can generate one with the Megawizard/ipcatalogue or manually instatiate one yourself (if you are familiar with using the altera_mf_components library and reading the documentation). 

 If you need code that is compilable on both altera and Xilinx, you have 2 options: 1. Make a wrapper around the dc fifo/xilinx fifo that uses a generic to differentiate the manufacturere) 2. Write your own DC fifo (you need to be really careful how you cross the clock domains).  The first option may be the easiest.

[Altera_Forum]

Thanks for you answer. But I need the possibilty to use this code also with devices not from Xilinx or Altera. The second option have a problem that I can't really know if my code will be without errors or optimized. So I ask if someone have an opensource Async FIFO.

[Altera_Forum]

You could try opencores.org

[Altera_Forum]

There's much on the web on this.  

E.g. http://www.iosrjournals.org/iosr-jvlsi/papers/vol1-issue3/e0133237.pdf