Avalon MM SLVERR(Slave Error) detail explanation.

[Basavakiran]

Hi,

from Avalon Specification sheet I'm not able to catch the proper data related to Avalon-MM SLVERR condition for "response" signal.

from Spec. sheet they mentioned description as "10: SLVERR—Error from an endpoint agent. Indicates an unsuccessful transaction." I want to know in which condition transaction will consider as unsuccessful to active SLVERR as a AMM-Slave in details.

from my understanding related to avalon-MM response signal as while write command time if any burstcount/address value got change before completion of full write transaction it will considered as unsuccessful transaction.
is this right case or not?

if right? then other then this is there any other conditions please drop me details.

Please can I get full in detail explanation related to "response" signal?.

[ShengN_Intel · Accepted solution]

Hi,

Yes, that's right. Other conditions will be like 1) Address or Data Errors if the endpoint agent receives an invalid or unrecognized address or data during a transaction. 2) Command issue protocol violations. 3) The endpoint agent itself may have internal error.

Thanks,

Best Regards,

Sheng

[Basavakiran]

Hello Sheng,

thanks for providing details.

I have one more doubt with "response".
in Avalon-MM writeresponsevalid and readdatavalid are different lines. if both are working parallel then response will get overlap so in that condition which operation response need to give higher priority?

eg: 1st I received a rd cmd with burstcount of 10 at 1st clock, from 2nd clock to 5th clock there will be a write cmd.
we are getting readdata and readdatavalid from 4th clock to 14th clock. as per specification writeresponsevalid need to sent next to wr transaction completion so writeresponsevalid need to sent at 6th clock. in this condition both wr and rd response will get overlap?

this is the senario you can consider.

Thanks & Regards
Basavakiran Hiremath 

[ShengN_Intel]

Hi,

Probably both wr and rd response will not get overlap. Check the document page 34:

Because the read and write interfaces share the response signal, an interface cannot issue or accept a write response and a read response in the same clock cycle.

Check also the timing diagram in page 35.

Thanks,

Best Regards,

Sheng

[Basavakiran]

Hi Sheng,

I got your point but my question is different.
is it possible to have a discussion over call based on your availability?
Please provide me your availability schedule so we can have a meeting. 

Thanks & Regards
Basavakiran Hiremath