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Block design

Altera_Forum
Honored Contributor II
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Hi, I have one bit output q[7] and I want connect this output to bus B[7..0] in block design file. It is possible? If yes, how? When I try it (I connect output directly to bus), compiler get error "Width mismatch...." . Thank you for your reply...

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Altera_Forum
Honored Contributor II
414 Views

 

--- Quote Start ---  

Hi, I have one bit output q[7] and I want connect this output to bus B[7..0] in block design file. It is possible? If yes, how? When I try it (I connect output directly to bus), compiler get error "Width mismatch...." . Thank you for your reply... 

--- Quote End ---  

 

 

Hi, 

 

you have to specify the name for the connection wire. If your output is the MSB of the bus, 

you have to use B[7].
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Altera_Forum
Honored Contributor II
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Thank you for you reply. I try it (picture OK). It is OK? I have next problem, when I try connect only one bit to bus output (pictures KO). How made this? 

Scheme is absurdity. It is only for problem preview...
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Altera_Forum
Honored Contributor II
414 Views

 

--- Quote Start ---  

Thank you for you reply. I try it (picture OK). It is OK? I have next problem, when I try connect only one bit to bus output (pictures KO). How made this? 

Scheme is absurdity. It is only for problem preview... 

--- Quote End ---  

 

 

Hi, 

 

you have to name the output of the multiplier e.g. result[15..0]. After that you can split a bit from the bus by naming the net e.g. result[7]. 

 

Kind regards 

 

GPK
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Altera_Forum
Honored Contributor II
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Thanks. This way is right? This solution in pin planer assign all outputs to pins. I want assign only output result[7]... Regards.

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Altera_Forum
Honored Contributor II
414 Views

 

--- Quote Start ---  

Thanks. This way is right? This solution in pin planer assign all outputs to pins. I want assign only output result[7]... Regards. 

--- Quote End ---  

 

 

That should work. As long as only result[7] is defined as output. 

 

Kind regards  

 

GPK
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Altera_Forum
Honored Contributor II
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Hi, 

 

It might work. But do one thing, please remove the connection between result[15..0] name and result[7]. Hence it will take only one bit also it wont show you all [15..0] pins in assignment editor. 

Please see the attachment. 

 

Regards, 

Jigar G. Shah
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Altera_Forum
Honored Contributor II
414 Views

Thanks, I try it.

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