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Modelsim simulation problem: altfp_mult floating point multiplier Megafunction

Altera_Forum
Honored Contributor II
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Hallo everybody, 

 

i have a problem when doing a functional simulation on Altera altfp_mult Megafunction: 

I configured the Megafunction to multiply two 32 bit floats with 5 clock cycles latency, and Modelsim shows me an unknown state of bits 30-23 after 2 clock cycles. However, the result after 5 clock cycles is correct. This behavior only occures with the first multiplication, if a change inputs after 5 clock cylces, i will get the right result without this strange behavior. 

The big problem ist that i want to cascade more multipliers and floating point adders for a PID controller, and if the first multiplication is wrong, the whole simulation will fail. 

 

I have implemented the multiplier on my Cyclon III Starter Kit and checkt the multiplier with Signal Tap. In rela life i could not monitor any strange behavior, so a guess that it is a simulation error, or that something is wrong with my simulation settings. 

 

 

Please see the attached picture of the simulation. I created the Megafunction with the Quartus II MegaWizard. My Modelsim projects include only the altfp_mult vhdl file and one testbench file to generate the clock an the stimuli. I will post this files and project settings if necessary. 

 

data_in_a and data_in_b are the inputs of the multiplier, res is the output. 

Signal clk is the clock signal. I hard-wired clk_en to '1' and aclr to '0'. Signals nan, ov, uv and zero a the flags of the multiplier. 

 

 

Can anybody tell me why this thing happens, and how can i avoid this behavior? 

 

Thanks in advance, 

magixD
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Altera_Forum
Honored Contributor II
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I don't exactly understand your problem. Clearly, with 5 clock cycle latency, there's no correct result before 5 cycles. The result may be also unknown in ModelSim.

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Altera_Forum
Honored Contributor II
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Try setting aclr to '1' for a couple clock cycles at the beginning of the simulation. If you have aclr hard-wired to '0', all the registers in the megafunction may not be getting set to a known value, thus, you see the x's.

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Altera_Forum
Honored Contributor II
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Thanks for you replies! 

 

@FvM: 

My problem is that i want the output to be 0X00000000 until the vlaid result is avaiable. I have cascaded many multipliers an adders, so anything other than '0' or '1' will mess up the whole simulation. 

 

@gmpstr: 

Thank you so much for that simple idea! If a reset the Megafunction for a couple of clock cycles, they behave like a want it. Thank you!
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Altera_Forum
Honored Contributor II
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anbody help me how to use altfp_mult without debug i have problem the resalt always is zero i donn't what is problem its a clock or for what what is the solution please help me

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Altera_Forum
Honored Contributor II
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Can you attach also the source code? Maybe there is only some bug in your code. You should not get 'X' values in your simulation.

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Altera_Forum
Honored Contributor II
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anbody have a sample design used bloc acceleratoer alltfp_mult and standard processor , JUST a shematic please it is urgent thank you

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Altera_Forum
Honored Contributor II
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send me a sample design use bloc accelerator altfp_mult linked with processor via pio .just a shemetic please hep me and thank you

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Altera_Forum
Honored Contributor II
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I don't want to be impolite (well, actually i don't care), but if you think you have to spam my thread, than describe your problem more precisely and learn how to write propertly! 

 

I don't know what you mean by "bloc accelerator", and I don't know what a "standard processor" is (since I know a ****load of different processor architectures), but if you want to connect a altfo_mult block to an GPIO port of a processor, the solution can't be that hard:
  1. you need two input ports that are connected to dataa and datab 

  2. you need one output port that is connected to result 

  3. you need to clock the multiplyer, either by a global clock or by an GPIO pin (depends on your application) 

  4. you need to connect the reset pin to an GPIO from your processor if you want to reset the altfp_mult by your software. if you dont need it, connect it to a logical low level 

  5. you need to connect the flag pins (underflow, overflow, nan,...) to GPIOs if needed, otherwise let them float.
If that does not work, post your code like ahmet already said. 

 

magixD
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Altera_Forum
Honored Contributor II
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hi ,THIS IS THE CODE C of multiplier c= a*b using altf_mult in megawizard quartus : 

 

void main( void

 

float a ,b,c=1; 

a=0x0EEEB0FF; 

b=0xE1EEE5FF; 

 

unsigned int EN; 

 

EN=0x01; 

 

 

 

IOWR_ALTERA_AVALON_PIO_DATA(PIO_A_BASE, a); 

IOWR_ALTERA_AVALON_PIO_DATA(PIO_B_BASE,b); 

IOWR_ALTERA_AVALON_PIO_DATA(PIO_EN_BASE,EN); 

 

//  

 

 

c=IORD_ALTERA_AVALON_PIO_DATA(PIO_RS_BASE); 

 

//  

printf("%f",c); 

 

 

 

thank you  

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Altera_Forum
Honored Contributor II
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please help me .IT IS urgent

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Altera_Forum
Honored Contributor II
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anyone can tell me how to use altf_mult megawizard with pio via nios correctly please , send me the code c if it is possible and thank you very match

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Altera_Forum
Honored Contributor II
1,276 Views

 

--- Quote Start ---  

Thanks for you replies! 

 

@FvM: 

My problem is that i want the output to be 0X00000000 until the vlaid result is avaiable. I have cascaded many multipliers an adders, so anything other than '0' or '1' will mess up the whole simulation. 

 

 

--- Quote End ---  

 

 

This will not be a problem. Inputs into other FPmults with 'X's will just cause output 'X's, but for 2 chained multipliers the result latency will be 10 clocks, and all output after 10 clocks will be valid, no matter what the indetermined state was. If this messes up the testbench, I think you may have designed the TB wrong. 

 

Why not have a 1 bit "valid" flag that runs parrallel to the data? you will need this (or a clock enable) if you have a bursty input anyway.
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