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I am able to successfully generate a design in Qys that includes the GHRD (General Hardware reference Design) plus a new module of my own.
My new module is coded in Verilog. It is linked in successfully in Qys as an Avalon MM (memory mapped) slave. I am able to generate the system in Qsys without errors. I can then successfully program the FPGA on an SoCKit development board. However I cannot see it in System Console after successfully programming the SoCKit development board. I can see and successfully read and write the standard LED and DIP switch modules. However my new module does not show up in System Console: % get_service_paths slave {/devices/5CSEBA6(.|ES)|5CSEMA6|..@1#USB 2-2.2#CV SoCKit/(link)/JTAG/fpga_only_master.jtag/phy_1/fpga_only_master.master/button_pio.s1} {/devices/5CSEBA6(.|ES)|5CSEMA6|..@1#USB 2-2.2#CV SoCKit/(link)/JTAG/fpga_only_master.jtag/phy_1/fpga_only_master.master/dipsw_pio.s1} {/devices/5CSEBA6(.|ES)|5CSEMA6|..@1#USB 2-2.2#CV SoCKit/(link)/JTAG/fpga_only_master.jtag/phy_1/fpga_only_master.master/intr_capturer_0.avalon_slave_0} {/devices/5CSEBA6(.|ES)|5CSEMA6|..@1#USB 2-2.2#CV SoCKit/(link)/JTAG/fpga_only_master.jtag/phy_1/fpga_only_master.master/jtag_uart.avalon_jtag_slave} {/devices/5CSEBA6(.|ES)|5CSEMA6|..@1#USB 2-2.2#CV SoCKit/(link)/JTAG/fpga_only_master.jtag/phy_1/fpga_only_master.master/led_pio.s1} {/devices/5CSEBA6(.|ES)|5CSEMA6|..@1#USB 2-2.2#CV SoCKit/(link)/JTAG/fpga_only_master.jtag/phy_1/fpga_only_master.master/onchip_memory2_0.s1} {/devices/5CSEBA6(.|ES)|5CSEMA6|..@1#USB 2-2.2#CV SoCKit/(link)/JTAG/fpga_only_master.jtag/phy_1/fpga_only_master.master/sysid_qsys.control_slave} % There should be one more, my new module called rf_4. A couple of things. When I call the programmer I call that from Quartus but in Quartus I don't see my new module in the hierarchy. I only see it when in Qsys. When I call System Console I can only call that from Qsys. I see the option in Quartus but there is no response. Any help for an Altera newbie much appreciated. Thanks MartinLink Copied
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