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Altera_Forum
Honored Contributor I
831 Views

Cannot simulate TSE - Design unit not found

Hello, 

 

I am trying to simulate my module from sopc using the triple speed ethernet ip.when I try to simulate I get the error 

"altera_tse_mac.v(376): Instantiation of 'altera_tse_top_gen_host' failed. The design unit was not found.# Region: /macb/b2v_inst/the_triple_speed_ethernet_0/altera_tse_mac_inst 

 

So i grabbed altera_tse_top_gen_host.v from the library and added to working directory and tried to compile... then i get this error 

 

Error: altera_tse_top_gen_host.v( 

syntax error, unexpected non-printable character 0x8b 

Error: altera_tse_top_gen_host.v( 

syntax error, unexpected $undefined, expecting "class" 

 

So I open up the file altera_tse_top_gen_host.v in notepad++ to see why its not reading the model and its....gibberish? Full of weird characters. Is this a fault in the altera library? Or is the v file meant to look like that.  

 

Thanks
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1 Reply
Altera_Forum
Honored Contributor I
57 Views

The tse Verilog file will be an encrypted IP core so it will look like gibberish when you open it. You will need a simulation model for it if there is one.

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