Clock enable design meets timing, but fails runtime

[Altera_Forum]

I have a 250Mhz clock generating a 125Mhz clock enable. All the logic runs of the 250Mhz with the 125Mhz clock enable at all registers. The design meets timing, but I see mixed results during runtime. SignalTap data looks inncorect and I see mixed results between compiles. For example, I'll post a snippet of code and the failing SignalTap screen shot.  

 The SignalTap shows the terminal_cnt changing on the rising and faling edge of the clk_125_ce, but some SignalTap samples will show the terminal_cnt changing only on the rising edge. The clock enable isn't working... The terminal counter doesn't even count by ones, it's all over the place.  It appears that the clk_125_ce isn't meeting timing or has place and route issue..... I'm completely stumped and this shouldn't be so difficult. Issues like this appear anywhere the clk_125_ce is used.  Code...  process (clk_250, reset, enable) begin  if clk_250 = '1' and clk_250'event then   if clk_125_ce = '1' then   if reset = '1' or enable = '0' then  terminal_cnt <= (others => '1');  else  if reg_write_1 = '1' then   terminal_cnt <= data_in(31 downto 0);  else   terminal_cnt <= terminal_cnt - 1;  end if;  end if;  end if;  end if;  end process;     tc <= '1' when terminal_cnt = "0000000000000000110" else '0';   SignalTap... https://www.alteraforum.com/forum/attachment.php?attachmentid=9292   Thanks for your advice!

[Altera_Forum]

What have to you connected to the clock input of signal tap? Also, what are ask these _tp signals? Rather than snippets, is much better to post the real code.

[Altera_Forum]

Ps. It is highly unlikely to be a place and route issue. I highly suspect user error somewhere.

[Altera_Forum]

The clock input for signal tap is the 250Mhz clock, but I also added the 125Mhz clock enable as a reference. All the _tp signals are the actual signals run through a register to ease timing. Helps with loading of signals for signaltap. 

 I would post more code, but the failures varies throughout the project. Should I be concerned about the phase relatationship of the 250 and 125 clock enable, or should the tool take care of that?  Is it possible a SDC constraint is causing this?

[Altera_Forum]

Are you getting some strange behavior/synthesis results because your enable and reset are in your sensitivity list but being treated synchronously to clk250 inside your process?

[Altera_Forum]

--- Quote Start ---  Are you getting some strange behavior/synthesis results because your enable and reset are in your sensitivity list but being treated synchronously to clk250 inside your process?  --- Quote End ---    I can remove the reset and enable from the sensitivity list and try the change. I do know that the reset and enable is not changing, causing the weird counting pattern.  Thanks, I give it a try. I stumped.

[Altera_Forum]

--- Quote Start ---  Are you getting some strange behavior/synthesis results because your enable and reset are in your sensitivity list but being treated synchronously to clk250 inside your process?  --- Quote End ---   As we all know, sensitivity lists are ignored in synthesis and matter in simulation only if they are missing signals. This is definitely not the problem.  The result doesn't match the claim of succesful timing analysis. Either you managed to cut some pathes in timing analysis, or the timing analysis assumptions are somehow wrong (e.g device speed grade, supply voltage, clock frequency and clock stability).