Converting To TIMEQUEST - "not_a_clock"

Altera_Forum · ‎09-09-2009

In converting to Timequest, I'm getting warnings about "altera_reserved_tck". I noticed in the classic analyzer that I had a "not_a_clock" setting against this signal and my notes indicate that it took care of the problems that the classic analyzer was spewing out at the time.

Do I get rid of these Timequest warnings in a smiliar way? I've read the "SDC and Timequest and API Reference Manual" but no mention of telling Timequest that the signal is <not> a clock.

Bill

Altera_Forum · ‎09-09-2009

@DiamondBill

are you sure that this signal is not used as a clock or generating a derived clock or gated clock in your design?

How many clocks do you have in your design?

Are all of the flip-flops and registers in your design solely clocked by external clocks?

Altera_Forum · ‎09-09-2009

There is no similar constraint because, "in theory" TimeQuest doesn't create clocks without a constraint, so if you don't constrain it to be a clock, it's not created.

That being said, I think derive_pll_clocks, which I recommend using, constrains this clock. Note that it is a real clock, as it's created by the JTAG controller(so something like SignalTap or Nios debugger runs off of it). That being said, it's not related to any other clocks in the design. I'm assuming your failing path has this as the clock for the source or destination register, but a different clock feeds the other one, so the problem is an incorrect clock relationship(all clocks are related by default in TimeQuest). You can unrelate it by doing:

set_clock_groups -asynchronous -group {altera_reserved_tck}

(Note that if you already have set_clock_groups in your .sdc, which I would also recommend, then add this as a separate group.

Altera_Forum · ‎09-09-2009

Sanmao,

I'm using multiple clocks from 1 pll in my desgin. Also have jtag and logic analyzer instance. All registers are being clocked by the pll derived clocks.

Rysc,

Thanks for the help - that worked. I don't understand why Timequest didn't capture the altera_reserved_tck when it converted my QSF file to the SDC file. I did find an interesting tidbit: I'm using SOPC and SOPC generates it's own SDC file. I opened up the file a moment ago to find this comment inside:

<begin quote># **************************************************************# Timequest JTAG clock definition# Uncommenting the following lines will define the JTAG# clock in TimeQuest Timing Analyzer# **************************************************************

# create_clock -period 10MHz {altera_reserved_tck}# set_clock_groups -asynchronous -group {altera_reserved_tck}

I think Altera needs to examine the default settings of their conversion tools.

So, now I get through recompilation/fitting/timequest with no errors pertaining to altera_reserved_tck --- but I get new timing errors having to do with:

altera_internal_jtag~TCKUTAP

I'm getting setup and hold violations in both fast and slow models. So, I will now attempt to determine if this is a clock and cut it from analysis the same with the altera_reserved_tck.

My question is why doesn't Altera have a custom SDC or TCL command to generate these JTAG clocks for us? Or has someone found a script on the web site that Altera has created?

Thanks guys for your help....

Bill