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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Cyclone 4 GX150 PLL compensation workaround

Altera_Forum
Honored Contributor II
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I'm trying to deserialize 6 different data channels with 6 different clocks in Cyclone 4 GX150. I have 8 PLLs in the device but still the tool gives error on one PLL if it tries to assign pins automatically. 

 

I remove all assignments and I start compilation. Even without any assignments the tool still gives error/critical warning with PLL compensation problem for some dedicated clock input pins  

 

=> is this mean a or b 

a)No matter how I assign the pins the device is not capable. Not possible 

b)Quartus tool is not so smart or have bugs while assigning dedicated clock inputs for PLLs. I still have a chance to remove the error by manually editing the location of dedicated clock
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