DDR3 variation file generation on Q10.1

[Altera_Forum]

Hi 

 BACKGROUND: I'm trying to compile a project to run on the Arria II GX development kit. the project includes an SOPC system with Nios DMAs and RAM. since the SRAM is too small I need to use the DDR3 memory. I've copied the DDR3 configuration from the example project and run my design (made sure to pass timing). everything looked ok except from the DMAs operation. I strongly believe this has something to do with the fact the the DDR3 local bus is 64 bit while my Nios and periphery are 32 bit.  PROBLEM when I try to change the parameter of the DQ bus width from the SOPC, it seems that only the SOPC changes, but the RAM.v variations file still shows 16 bit DQ bus. this causes mismatch errors in synthesis.  when I try to change it through the Mega Wizard editor, it changes a wrapper file, but not the variation file...  any ideas?

[Altera_Forum]

Things are getting stranger: 

I reinstalled the evaluation board kit, and opened the example (board update portal) project. then I generated the SOPC system, and I noticed that the sdram.v was not created. other files such as sdram_alt_ddrx_controller_wrapper.v and sdram.ppf (what ever this file do ) were created. It seems that all of the other components (sgdma, cpu, tse_mac) don't have any problems.  one more important thing, when the SOPC starts up (or when I refresh the system) I get a warning: Warning: altmemddr3: Catalog mismatch; expected v10.1 but found v10.0  on my machine I have version 8.1, 10.1 and 12.0 so I don't see why only the DDR3 will find that particular version, and whether or not it should make a difference.

[Altera_Forum]

I feel like I'm talking to myself... 

 Anyway, the problem is solved, reinstalled Q10.1 and everything started to play.