Embedded Multiplier vs Logic Elements

Altera_Forum · ‎05-23-2011

Hi everybody,

I have a question on the synthesis of a multiplier written in VHDL.

I have a module (in VHDL) which uses several multipliers. But when I run the Quartus compilation, thoses multipliers are synthesized into "Logic Elements" and not into "Embedded Multiplier 9-bit elements"...

How can I "force" Quartus to generate my multipliers into Embedded Multiplier?? (I have lot of Embedded Multiplier elements available so it is not a limitation due to my FPGA..)

Thanks!!

Altera_Forum · ‎05-23-2011

You can set a synthesis attribute on architecture level. Follow the description in the Quartu software handbook.

architecture rtl of MyUnit is
attribute multstyle : string;
attribute multstyle of rtl : architecture is "dsp";