Equivalent to assert for Quartus compile (Verilog source)

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Equivalent to assert for Quartus compile (Verilog source)

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Hi,

is there a way to force a compile error and generate a user message using Verilog source (not System Verilog)? Sort of equivalent to an assert macro in C.

This would be really useful in cases where I have created a re-usable module which will only work if parameters are within prescribed ranges, for example.

Thanks,

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