Error in Generating Testbench [Platform Designer] can't read "intf" no such element in array

[Test998]

Hello,

   I am trying to simulate PCIe_DDR4 example provided for Terasic DE5a-NET DD4. I have made a modification to the project. After opening it in Quartus Prime Pro [linux: 22.4.0] and going to Platform Designer [22.4 Build 94] I add a custom counter logic as a component and an Avalon FIFO [altera_avalon_fifo] in the System Viewer. Just the counter and the FIFO together were simulated in ModelSim and found to be working correctly.

The Avalon FIFO will connect to the pipe stage [altera_avalon_mm_bridge]  and write data to the DDR4 memory. I want to verify this in simulation before proceeding to hardware verification. After adding the components and the IP, in platform designer, and performing `Sync-System-Infos` -> `Validate System Integrity` -> 'Generate HDL'. I did `Generate Testbench System` where it ends with the following error:  ` can't read "intf_use_partner(npor)" no such element in array`.

How can I solve this problem?

I am using Quartus Prime Pro in Ubuntu 22.04.

Quartus Prime version 22.04 Build 94 12/07/2022 SC Pro Edition

Platform Designer 22.4 Build 94

Please let me know if you would like to have any more information

[ShengN_Intel]

Hi,

Seems like an expected behavior on pcie and ddr system check this similar post link community.intel.com/t5/FPGA-Intellectual-Property/run-AN708-on-Quartus-21-3/m-p/1414713#M26315:

when generate testbench system.  

Error: can't read "intf_use_partner(pcie_rstn)": no such element in array

Error: Error: can't read "intf_use_partner(pcie_rstn)": no such element in array

Error: There were errors creating the testbench system.

For further detail, may be can open a new thread target pcie and ddr field.

Thanks,

Best Regards,

sheng

[ShengN_Intel]

Hi,

Any further update or concern?

Thanks,

Best regards,

Sheng