Error in altera modelsim

[Altera_Forum]

Hello guys, i have a problem with simulation in altera modelsim about serial input parallel output shifter register 

 vhdl code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity sipo1 is port ( clk : in STD_LOGIC; reset: in STD_LOGIC; D : out unsigned(7 downto 0) ); end sipo1; architecture behavioral of sipo1 is signal temp : unsigned(7 downto 0) := (others => '0'); begin D <= temp; process (clk) begin if (rising_edge(clk)) then if (reset = '1') then temp <= (0 => '1', others => '0'); else temp(1) <= temp(0); temp(2) <= temp(1); temp(3) <= temp(2); temp(4) <= temp(3); temp(5) <= temp(4); temp(6) <= temp(5); temp(7) <= temp(6); temp(0) <= temp(7); end if; end if; end process; end behavioral;   testbench: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY sipo1_tb IS END sipo1_tb; ARCHITECTURE behavioral OF sipo1_tb IS -- constants -- signals SIGNAL clk : STD_LOGIC:= '0'; SIGNAL D : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL reset : STD_LOGIC:= '0'; constant clk_period : time := 20 ns; COMPONENT sipo1 PORT ( clk : IN STD_LOGIC; D : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); reset : IN STD_LOGIC ); END COMPONENT; BEGIN uut : sipo1 PORT MAP ( -- list connections between master ports and signals clk => clk, D => D, reset => reset ); clk_process : PROCESS -- variable declarations BEGIN -- code that executes only once clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; END PROCESS; sipo1_1 : PROCESS -- optional sensitivity list -- ( ) -- variable declarations BEGIN -- code executes for every event on sensitivity list reset <= '1'; wait for 4 ns; reset <= '0'; wait for 5 ns; reset <= '1'; wait for 2 ns; reset <= '0'; wait; END PROCESS sipo1_1; END behavioral;   the error is "PAUSED AT LINE 12", in the next script, I show more detailed error  # Reading C:/altera/15.0/modelsim_ase/tcl/vsim/pref.tcl# do sipo1_run_msim_rtl_vhdl.do# if {} {# vdel -lib rtl_work -all# }# vlib rtl_work# vmap work rtl_work# Model Technology ModelSim PE vmap 10.3d Lib Mapping Utility 2014.10 Oct 7 2014# vmap -modelsim_quiet work rtl_work # Copying C:/altera/15.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini# Modifying modelsim.ini# ** Warning: Copied C:/altera/15.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini.# Updated modelsim.ini.# # vcom -93 -work work {C:/Users/SAULO/Downloads/PROYECTOS FPGA/Tarea/sipo1/sipo1.vhd}# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014# Start time: 10:29:17 on Nov 25,2015# vcom -reportprogress 300 -93 -work work C:/Users/SAULO/Downloads/PROYECTOS FPGA/Tarea/sipo1/sipo1.vhd # -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Loading package NUMERIC_STD# -- Compiling entity sipo1# -- Compiling architecture behavioral of sipo1# End time: 10:29:18 on Nov 25,2015, Elapsed time: 0:00:01# Errors: 0, Warnings: 0# # vcom -93 -work work {C:/Users/SAULO/Downloads/PROYECTOS FPGA/Tarea/sipo1/simulation/modelsim/sipo1_tb.vhd}# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014# Start time: 10:29:18 on Nov 25,2015# vcom -reportprogress 300 -93 -work work C:/Users/SAULO/Downloads/PROYECTOS FPGA/Tarea/sipo1/simulation/modelsim/sipo1_tb.vhd # -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Compiling entity sipo1_tb# -- Compiling architecture behavioral of sipo1_tb# End time: 10:29:20 on Nov 25,2015, Elapsed time: 0:00:02# Errors: 0, Warnings: 0# # vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneive -L rtl_work -L work -voptargs="+acc" sipo1_tb# vsim -gui "+altera" -l msim_transcript -do "sipo1_run_msim_rtl_vhdl.do" # Start time: 10:29:20 on Nov 25,2015# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.sipo1_tb(behavioral)# Loading ieee.numeric_std(body)# Loading work.sipo1(behavioral)# ** Failure: (vsim-3807) Types do not match between component and entity for port "D".# Time: 0 ps Iteration: 0 Instance: /sipo1_tb/uut File: C:/Users/SAULO/Downloads/PROYECTOS FPGA/Tarea/sipo1/sipo1.vhd Line: 9# Fatal error in file C:/Users/SAULO/Downloads/PROYECTOS FPGA/Tarea/sipo1/sipo1.vhd# while elaborating region: /sipo1_tb/uut# Fatal error in file C:/Users/SAULO/Downloads/PROYECTOS FPGA/Tarea/sipo1/simulation/modelsim/sipo1_tb.vhd# while elaborating region: /sipo1_tb # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./sipo1_run_msim_rtl_vhdl.do PAUSED at line 12   any solution? please :(

[Altera_Forum]

--- Quote Start ---  Failure: (vsim-3807) Types do not match between component and entity for port "D".  --- Quote End ---   you have difference in entity and component declaration -> please check. You can use different order of ports while instaining component but do not do this in component declaration. meanwhile you testbench cover only 'reset' signal and make meanigful comments. you have process with signal 'clk' but comment as 'execute only once'.

[Altera_Forum]

When instaining component use always named association for formal and real parameters. try avoid association by position or better forget forever. 

when declaring component just simply copy entity defintion and proper replace 'entity' keyword with 'component' according to VHDL syntax.

[Altera_Forum]

D is unsigned and you declared as std_logic_vector?

[Altera_Forum]

You declare the entity port D as unsigned but in the component declaration it is a std_logic_vector

[Altera_Forum]

this looks like a job for my Altera support. Please go ahead and file this and let them solve this for you. Free of charge

[Altera_Forum]

--- Quote Start ---  this looks like a job for my Altera support. Please go ahead and file this and let them solve this for you. Free of charge  --- Quote End ---    No it doesnt. There is a type missmatch. Its not a modelsim bug (which is a mentor product anyway, not altera)

[Altera_Forum]

Tricky is right. Modelsim is a product of Mentor. Altera might refer you back to Mentor.