Extra timing paths in Timequest on DDR source sync

[Altera_Forum]

Hi, 

 I am doing a DDR source sync LVDS interface with FPGA as transmitting device. The clock is centre aligned.   I have referred to Rysc's examples (Thanks Rysc!) on how to constrain DDR source sync interfaces and think I am pretty much sorted. I understand how the arrival and required paths work and everything looks good. However, I have one point that I don't understand.   In the setup report of my generated source sync report I have four entries for each data pin. I have 1) rise launch clock, rise latch clock; 2) fall launch clock, fall latch clock; 3) rise launch clock, fall latch clock; 4) fall launch clock, rise latch clock;   Is this normal? I was only expecting 1) and 2).   Here is my .sdc   ------Start of .sdc -----------------# Create input clock create_clock -period 10 -name PLL_ref [get_ports {pll_ref_clk}]  # Create DDIO data clock  create_generated_clock -name lvds_clk -source pll_ref_clk -multiply_by 3 [get_nets {lvds_pll_i|altpll_component|auto_generated|wire_pll1_clk[0]}] # Create DDIO Clock 90deg shifted create_generated_clock -name out_clk -source [get_ports {pll_ref_clk}] -multiply_by 3 -phase 90 [get_nets {lvds_pll_i|altpll_component|auto_generated|wire_pll1_clk[1]}] # Create generated clock for Source Sync Output create_generated_clock -name disp_clk -source [get_nets {lvds_pll_i|altpll_component|auto_generated|wire_pll1_clk[1]}] [get_ports {disp_clk}]  # Set output delays set_output_delay -max -clock { disp_clk } 0.2 [get_ports {dis_data*}] set_output_delay -min -clock { disp_clk } -0.2 [get_ports {dis_data*}] set_output_delay -max -clock { disp_clk } 0.2 [get_ports {dis_data*}] -clock_fall -add_delay set_output_delay -min -clock { disp_clk } -0.2 [get_ports {dis_data*}] -clock_fall -add_delay  # set false path set_false_path -from *|altddio_out:altddio_out_component|*  ----end of .sdc-----------   I have included a picture as well.   Thanks in advance for your time.   C