How good is the inferred multiplier?

[Altera_Forum]

I am working with a previous developers verilog code set and looking for places to improve speed/area within their design. The majority of their development is behavioral, including one such statement 'a=b*c'. Is it safe to assume that the synthesizer will infer an optimal multiplier for the chip (a cyclone III, in this case), or is it worth considering the design of my own multiplier? Also, I am aware that the multiplier is an ip core within quartus, but using the ip core defeats the purpose of the exercise.  

 Thanks in advance.

[Altera_Forum]

You should consider Cyclone III's hardware multipliers as optimal solution in terms of speed and area. They are typically used for inferred multipliers, as longs as you have enough free resources. If you run short of it, Quartus can be expected to select hardware multipliers where needed according to timing requirements. If you don't agree with it's choice, you can change the selection for modules or individual blocks by a "multiplier style" synthesis attribute. See the Quartus software manual for details.

[Altera_Forum]

Inferring multiupliers is usually fine, aslong as you stay within the hardware limits (which for all Altera FPGAs is 18 bits per input - you can do up to 36 bits per inputs but you'll see your multipliers dissapear quite quickly) 

 It should pick up registers from the code that are contained inside the DSP slice too.