FIFOED Avaloun UART and DMA with QSYS

[Altera_Forum]

Hi  

 I have a legacy design that was generated using Quartus 8.1. the design includes SOPC builder system that uses the FIFOED Avalon UART version 9.3. recently I've upgraded to Quartus 12.0 sp2. that caused some logic problems when I used the DMA, to read from the RX FIFO. I solved the problem by instantiating the FIFOED UART outside of the SOPC builder system, and inserting some glue logic. now I wanted to upgrade to QSYS instead of SOPC Builder (still with 12.0 sp2) but it seems that the data available signal is totally ignored, since the UART don't have a wait request signal.  a few questions: Is there a new release of the FIFOED Avalon UART? Is there documentation of back compatibility issues with the old Avalon bus spec? Is there a standard work around?

[Altera_Forum]

Hi, 

 I do not know if you figure out a solution. I am interested in hearing about your design. I am adding a UART to a 13.0sp1 design. There seems to be two options available, a free one Avalon UART and a purchased one UART_16550. Both seem to need a DMA connected be used in a full system. The UART_16550 has a small TX and RX FIFO 16 bytes, but this would still but too big a load on the NIOS. Any reference designs for UART and DMA?   Thanks