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Fan-out: how high is too high? (Stratix II)

Altera_Forum
Honored Contributor II
‎04-13-2009 08:53 PM
1,272 Views

We have Stratix II FPGA in one of our design. After compilation, fan-out for a global clock goes beyond 30,000, and several non-global pins have fan-out in the range of 3000 ~ 5000. 

 

Is this too high?? Has anyone experienced problem associated with high fan-out? Could this overheat and potentially damage the chip? 

 

Thanks, 

fan
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Altera_Forum
Honored Contributor II
‎04-14-2009 03:06 AM
501 Views

A global is designed to feed every register in the device, so this is perfectly fine. 

High-fanout is not a problem in the FPGA because routing lines are re-buffered all over the place. If you're not using a global for a high-fanout clock line, you can have skew issues, but timing analysis will alert you to that. As for overheating, it's not directly related to fanout, but amount of logic and toggle rates, amongst other things.  

 

The main point is it's absolutely fine.
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Altera_Forum
Honored Contributor II
‎04-14-2009 04:34 AM
501 Views

Thanks very much. This is very comforting.

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