I just started learning VHDL. The syntax I already have an my code is correct according to research I have done, but I keep getting this error that won't let me synthesis my code. I have pasted my code for you to look at. I am trying to turn on LED 15 of a NEXYS 4 when a person flips the switch. As a side note if anyone knows any resource to help learn VHDL that would be much appreciated.
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/09/2016 01:21:54 PM
// Design Name:
// Module Name: LED15
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LED15(
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity my_entity is
port(
switch : in STD_LOGIC;
light_LED : out STD_LOGIC
);
end my_entity;
architecture Behavioral of my_arch of my_entity is
begin
if (switch = 1) then
port_light_LED <= '1';
end if;
end Behavioral;
